About this role
RFIC Silicon Lead at Tacit. Location: San Francisco, California, United States. Role: defining architecture, designing circuits, directing tapeout Requirements: MS/PhD in EE (or equivalent), 10+ years RFIC design delivering silicon, deep low-power CMOS RF and synthesizer expertise, transistor-level Cadence Virtuoso/ Spectre/ ADE experience, EM simulation experience, strong communication and technical leadership. Category: Engineering Seniority: Senior Level Tools: Cadence Virtuoso, Spectre, ADE, EMX, HFSS, Momentum, Calibre, PDK Commitment: Full Time Workplace: Onsite Languages: English