About this role
Design Engineer at Lumilens. Location: San Jose, California, United States. Role: designing RTL, writing testbenches, debugging simulation Requirements: BS/MS in Electrical/Computer Engineering (or equivalent), 3+ years SystemVerilog RTL design experience, strong digital design fundamentals, power/timing-aware practices, simulation debug, and scripting in Python/Perl/TCL. Category: Engineering Seniority: Mid Level Tools: SystemVerilog, Python, Perl, TCL, UVM, SVA Commitment: Full Time Workplace: Onsite Languages: English