About this role
Senior FPGA Engineer (Verilog/Alveo U45N) at Tnsi. Location: Budapest, Budapest, Hungary. Role: architecting designs, optimizing latency, mentoring engineers Requirements: Expertise in AMD/Xilinx FPGA development (UltraScale+), Vivado tool flow, Verilog/SystemVerilog, Linux, high-speed network interfaces, and FPGA NIC frameworks; bachelor’s/master’s in EE/CE or equivalent senior experience. Category: Engineering Seniority: Senior Level Tools: AMD Alveo U45N, Vivado Design Suite, Vivado Simulator, ModelSim, Questa, Verilog, SystemVerilog, OpenNIC, QDMA, Linux, Python, C, C++ Commitment: Full Time Workplace: Onsite Languages: English