FPGA Silicon Design Verification Engineer @ Altera

FPGA Silicon Design Verification Engineer at Altera. Location: Bengaluru, Karnataka, India. Role: verifying designs, developing tests, debugging issues Requirements: 7+ years verifying FPGA designs using SystemVerilog and UVM/OVM, scripting with Perl/Python, experience with RTL simulation, regression testing, coverage and debugging pre-silicon issues. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, OVM, Perl, Python Commitment: Full Time Workplace: Onsite Languages: English