About this role
Lead Real-Time Digital Systems & Hardware-in-the-Loop (HIL) Testbed Engineer at GMV. Location: Gilching, Bavaria, Germany. Role: leading design, implementing HIL, integrating systems Requirements: Advanced degree in EE/Telecom/Computer Engineering/Physics, strong FPGA and real-time digital systems experience (VHDL/Verilog/SystemVerilog), FPGA platforms (Xilinx/Intel), Python/MATLAB, signal processing and SatCom knowledge. Category: Engineering Seniority: Senior Level Tools: VHDL, Verilog, SystemVerilog, AMD/Xilinx, UltraScale+, RFSoC, Versal, Intel Agilex, PCIe, Ethernet, JESD204, DMA, Python, MATLAB, SDR, GPU, DPU, SmartNICs, ARM, Linux Commitment: Full Time Workplace: Hybrid Languages: English