About this role
System Verification Co-Design Engineer - Speed and Rel at NVIDIA. Location: Santa Clara, California, United States. Role: collaborating cross-functionally, designing automation, leading debug Requirements: MS in EE/CE/Systems or equivalent, 4+ years hardware engineering experience, silicon bring-up and PPA analysis, scripting in Python/Perl, lab instrumentation, statistical methods, and demonstrated use of AI/LLM tools in engineering workflows. Category: Engineering Seniority: Mid Level Tools: Python, Perl, Windows, Linux, Android, JMP, Claude, Copilot, ChatGPT, LLM Commitment: Full Time Workplace: Onsite Languages: English