About this role
DSP Engineer at SWISSto 12. Location: New York or New Jersey or United States. Role: designing algorithms, implementing fpga, debugging hardware Requirements: MS in Electrical Engineering (DSP focus) required; 7+ years FPGA design with synthesizable RTL, VHDL/Verilog/SystemVerilog, Vivado/Vitis toolchains, high-speed serial interfaces (JESD204B/C, PCIe, Ethernet), SOC/FPGA platforms, and strong lab debugging skills. Category: Engineering Seniority: Senior Level Tools: Vivado, Vitis, VHDL, Verilog, SystemVerilog, JESD204B, JESD204C, PCIe Gen3, PCIe Gen4, Ethernet, Aurora, AMD RFSoC, Zynq Ultrascale+, Versal AI Core, Microchip PolarFire, AXI Commitment: Full Time, Contract Workplace: Remote Languages: English