About this role
Senior FPGA Engineer at Plessey Semiconductors. Location: Oxford, Oxfordshire, United Kingdom. Role: designing RTL, verifying designs, leading bring-up Requirements: Degree in electronic/computer engineering or physics, strong RTL design in VHDL or Verilog/SystemVerilog, high-speed serial and clock-data-recovery experience, verification and timing-closure skills, FPGA bring-up and debug. Category: Engineering Seniority: Senior Level Tools: VHDL, Verilog, SystemVerilog, HDMI, Altium, HyperLynx, Ansys SI, ADS Commitment: Full Time Workplace: Onsite Languages: English