About this role
Sr. FPGA /CPLD Engineer (Server & Storage-三重) at Jabil. Location: Sanchong, New Taipei City, Taiwan. Role: developing designs, validating designs, designing tests Requirements: 3+ years CPLD/FPGA development, Verilog/VHDL/System Verilog and RTL experience, familiarity with I2C, SPI, UART, SGPIO, Git, UVM a plus; EE degree or equivalent experience; strong English communication and teamwork. Category: Engineering Seniority: Mid Level Tools: Verilog, VHDL, System Verilog, RTL, I2C, SPI, UART, SGPIO, Git, UVM Commitment: Full Time Workplace: Onsite Languages: English