About this role
Logic Lead at Flir. Location: Pune, Maharashtra, India. Role: designing RTL, leading engineers, debugging hardware Requirements: Bachelor's/Master's in Electrical or Computer Engineering, 8+ years FPGA/RTL design experience, expert SystemVerilog/Verilog/VHDL, experience with Xilinx/Intel FPGA families, wireless protocol knowledge, UVM and hardware debug experience. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, Verilog, VHDL, Vivado ILA, SignalTap, UVM, Python, C/C++, MATLAB, AMD Xilinx (UltraScale+), Versal, Intel Altera, Stratix, Agilex, GTY, PCIe, USB 3.0, DDR4, DDR5 Commitment: Full Time Workplace: Onsite Languages: English