About this role
Analog Layout Engineer at Nokia. Location: Zhubei City, Hsinchu County, Taiwan. Role: editing layout, performing DRC/LVS, creating powergrid Requirements: 5+ years analog/mixed-signal layout experience, expertise with Virtuoso, Calibre and LVS/DRC/ERC flows, FinFET layout (7nm/5nm), power integrity/EM/IR knowledge, and ability to collaborate with circuit designers. Category: Engineering Seniority: Senior Level Tools: Virtuoso, Calibre, PVS, IC Validator, pCell, pyCell Commitment: Full Time Workplace: Onsite Languages: English