About this role
<p style="margin:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Job Title: Senior Specialist, Electrical Engineering (FPGA Digital Design Engineer)</span></strong></p> <p style="margin:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Job Code: 38228</span></strong></p> <p style="margin:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Job Location: Fort Wayne, IN</span></strong></p> <p style="margin:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Job Schedule: 9/80 Regular<br><br></span></strong></p> <p style="margin:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Job Description: </span></strong></p> <p style="margin:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">Responsible for developing FPGA Firmware in the Space & Mission Systems (SMS) Segment of L3Harris. The SMS Segment provides critical mission solutions for space and airborne domains with defense, intelligence, and commercial applications. As an FPGA design engineer, you will be directly involved in one or more of the areas of design, integration, and test of advanced satellite communication links, digital telemetry, signal processing, and/or encryption technology.</span></p> <p style="margin:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black"><br>Essential Functions: </span></strong></p> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">Support proposal efforts in the estimation and planning of end-to-end FPGA development.</span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">Decompose and allocate system and box-level requirements to FPGA requirements and specifications.</span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">Architect solutions against requirements and implement those solutions in various FPGA technologies or platforms.</span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">Design Med/High Complexity Field Programmable Gate Array (FPGA) starting from System</span><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif"> </span><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">De-composition and completing through System Integration and Test</span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">Follow, enforce, and refine consistent firmware development processes across FPGA designs.</span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">Synthesize designs to targeted technologies and perform constraint driven place and route and analysis.</span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">Generate design review and deliverable documentation including review packages, block diagrams, interface control documents, and test plans/procedures.</span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">Conduct design peer reviews at various phases in the development process.</span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">Ensure FPGA simulations verify performance, then integrate and test the FPGA on the circuit card assembly.</span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">Generate verification plans and procedures to validate hardware.<br>Perform hardware testing and debug.</span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">Ability to obtain a Secret clearance </span><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif"><br><br></span></li> </ul> <p style="margin:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Qualifications: </span></strong></p> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">Bachelors of Science Degree in Electrical/Computer Engineering with 6 years' professional experience or a Graduate degree and a minimum of 4 years' relevant professional experience. In lieu of a degree, minimum of 10 years' of prior related experience</span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">6+ years experience using VHDL/Verilog</span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">6+ years experience with and understanding of AMD Xilinx FPGA architectures </span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">3+ Years of professional experience with Xilinx Vivado</span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">3+ years experience performing timing closure, optimizing FPGA resource utilization</span></li> <li style="color:black;margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:windowtext">3+ years experience debugging down to the hardware level, using Signal Generators, Logic Analyzers, Digital Oscilloscopes and Embedded FPGA Debugging tools</span></li> </ul> <p style="margin:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"> </p> <p style="margin:0.0in;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Preferred Additional Skills:</span></strong></p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">FPGA development and Verification Vendor tool suites: Xilinx ISE, Xilinx Vivado, Xilinx Vitis, Microchip Libero, Mentor Graphics ModelSim/Questa, Synopsis Synplicity</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">Version Control tools such as GIT, SVN, CVS.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">Experience with advanced verification environments such as UVM & OVM</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">Experience using System Verilog for verification </span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">Build FPGAs with difficult timing and/or difficult routing constraints</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">Develop FPGA requirements and specifications</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">FPGA Device Selection and supporting the Pinout on a new CCA Design</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">High speed memory interfaces and/or high speed SERDES interfaces</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">Analog to Digital (AD) and Digital to Analog (DA) interfaces</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">Experience with AXI streaming and control buses</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">Possess the ability to interface with Hardware, Software, and Systems Engineering</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">Self-motivated individual with the ability to work and communicate effectively within a development group</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">Bring-up of advanced FPGA products such as SoC, MPSoC, RFSoC, ACAP, etc.</span></li> <li style="margin:0.0in 0.0in 8.0pt 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">Digital Circuit Card Design: Schematic Entry, PCB/PWB Layout/Route, Signal Integrity Analysis.</span></li> </ul> <p style="margin:0.0in 0.0in 8.0pt;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black"> </span></strong></p> <p style="margin:0.0in 0.0in 8.0pt;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:white">#LI-KB1</span></p>