About this role
<p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><em>Job Title: Specicliat, </em></strong><strong><em>Systems Engineer </em></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><em>Job Code: </em><em><em>40396</em></em></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><em>Job Location: </em></strong><strong><em>Salt Lake City, UT</em></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><em>Job Schedule: </em></strong><strong><em>9/80 Employees work 9 out of every 14 days- totaling 80 hours working- and have every other Friday off <br><br><br><br></em></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Description:</strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>We are seeking an experienced Systems Engineer, Specialist to support critical test and integration activities as the Lead Systems Verification Engineer for advanced communication systems programs. This role requires an engineer capable of managing multiple complex technical issues simultaneously, coordinating cross-functional failure review boards (FRBs), and driving resolution of system-level anomalies through root cause analysis and corrective action implementation. This position offers the opportunity to work on cutting-edge communication systems with direct impact on national defense capabilities. The ideal candidate thrives in dynamic environments where technical expertise, leadership, and communication skills are essential to mission success.<br><br><br><br></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Essential Functions:<br><br><br></strong></span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Coordinate simultaneous execution of multiple test programs including HALT (Highly Accelerated Life Testing), ESS (Environmental Stress Screening), ATP (Acceptance Test Procedures), and EME (Electromagnetic Environmental Effects) testing</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Validate test procedures and data analysis methods against specification requirements</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Serve as Cost Account Manager (CAM) for assigned test and integration work packages</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Monitor and report cost performance using Earned Value Management System (EVMS) metrics (BCWS, BCWP, ACWP, CPI, SPI)</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Interface with Program Management Office (PMO) for procurement of critical test equipment and materials</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Oversee DVT (Design Verification Test) report generation and technical documentation</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Coordinate with cross-functional teams including design engineering, manufacturing, and quality assurance</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Manage test resource allocation and scheduling conflicts across parallel test activities</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Up to 5% travel required</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Have an Active DoD Secret Clearance </strong></span></li> </ul> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><br><br><br>Qualifications:<br><br><br></strong></span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Bachelor's degree in Systems Engineering, Electrical Engineering, Computer Engineering, or related technical field with 4 years of experience, or a Master’s degree with 2 years of experience</strong></span></li> </ul> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><br><br>Preferred Additional Skills:<br><br><br></strong></span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Active Secret or Top Secret security clearance</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Must be a U.S. Citizen and able to obtain/maintain required clearance</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Strong understanding of RF/microwave systems, including transmitter/receiver architectures</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Knowledge of environmental testing standards (MIL-STD-810, DO-160, or similar)</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Experience with EMI/EMC testing and electromagnetic environmental effects analysis</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Strong analytical and problem-solving skills with attention to detail</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Excellent written and verbal communication skills for technical presentations</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Experience working with prime contractors and government customers</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Ability to work effectively under pressure with competing deadlines</strong></span></li> </ul> <p><span style="color:white;font-family:verdana, geneva, sans-serif;font-size:14.0pt">#LI-JD3 </span></p>