About this role
<p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><em>Job Title: Specialist, </em></strong><strong><em>Systems Engineer </em></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><em>Job Code: </em><em><em>40392</em></em></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><em>Job Location: </em></strong><strong><em>Salt Lake City, UT</em></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><em>Job Schedule: </em></strong><strong><em>9/80 Employees work 9 out of every 14 days- totaling 80 hours working- and have every other Friday off <br><br><br><br></em></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Description:<br><br><br><br></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>We are seeking a Systems Engineer for the SF2 program to provide technical leadership across system development, integration, verification, and customer-facing execution for complex communication systems. This role will work across software, test, lab, and external partner teams to drive requirements alignment, integration readiness, technical risk reduction, and successful execution of key program milestones. <br><br><br><br><br></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Essential Functions:<br><br><br><br></strong></span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Lead system-level planning, integration, and verification activities in a development environment coordinating the efforts of cross-functional engineering teams</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Guide requirements development, traceability, decomposition, and validation to ensure alignment between design, implementation, and verification test coverage </strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Support technical baseline management, interface definition, configuration alignment, and readiness for major reviews and milestone events</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Prepare and present technical status, risks, and recommendations to program leadership, customers, and partner organizations.</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Help identify and mitigate system-level technical, schedule, and integration risks.</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Up to 5% travel required</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Have an Active DoD Secret Clearance </strong></span></li> </ul> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><br><br><br><br>Qualifications:<br><br><br><br></strong></span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Bachelor's degree in Systems Engineering, Electrical Engineering, Computer Engineering, or related technical field with 4 years of experience, or a Master’s degree with 2 years of experience</strong></span></li> </ul> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><br><br><br>Preferred Additional Skills:<br><br><br><br></strong></span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Active Secret or Top Secret security clearance</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Must be a U.S. Citizen and able to obtain/maintain required clearance</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Experience in systems engineering, system integration, verification and validation, or technical program execution.</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Strong ability to lead cross-functional problem solving in complex technical environments.</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Strong written and verbal communication skills, including experience preparing technical briefings and status updates.</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Ability to work independently and lead coordination across engineering, test, and program teams.Experience working with prime contractors and government customers</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Ability to work effectively under pressure with competing deadlines</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Experience with requirements management, traceability, interface control, and system architecture development.</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Experience leading integration and verification efforts for communications systems</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Familiarity with developmental test, qualification test, over-the-air testing, and lab-based system bring-up.</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Experience with technical risk management, milestone planning, and customer or supplier coordination.</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Working knowledge of defect tracking, configuration management, test procedure development, and structured verification methods.</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Ability to mentor team members, drive technical decisions, and translate high-level program goals into executable engineering plans.</strong></span></li> </ul> <p><span style="color:white;font-family:verdana, geneva, sans-serif;font-size:14.0pt">#LI-JD3 </span></p>