Job Title: Associate, FPGA / ASIC Verification Engineer Job Code: 40384 Job Location: Cincinnati, OH Job Schedule: 4/10: Employees work 10 hour days, 4 days a week Job Description: As an Associate ASIC/FPGA Verification Engineer at L3Harris you will be responsible for verifying the architecture, design and implementation of next generation Electronic Safe and Arm Devices utilizing the latest state of the art tools and technologies. The ideal candidate for this role would share our passion for creating and innovating new technologies in a highly dynamic, fast-paced environment. We are looking for highly talented, motivated, and versatile engineers that can create the next generation fuzing solutions. ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A interfaces, communication protocols, state machines, timer chains, etc. used in Electronic Safe and Arm Devices (Fuzes) for DOD weapon systems. <a name="_Hlk171607763"></a>Microchip/Microsemi Antifuse and Flash are our targeted FPGAs with occasional ASIC development, Siemens Mentor Graphics QuestaSim Prime is our simulation tool, and the System Verilog UVM framework is the current verification environment. The primary responsibilities will focus on Verilog FPGA design verification, and the System Verilog UVM framework verification. Essential Functions: <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Analysis of the requirements, architecture definition, design and debug of FPGA and associated hardware and microcontroller products and associated firmware.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Developing Verilog HDL targeting Antifuse and enhanced Flash FPGAs.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Developing C# source code targeting enhanced Flash Microcontrollers.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Performing effective analysis of functional issues or performance profiling with the hardware and firmware in test environments or target host systems.</li> </ul> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Contribute to process improvements to ensure hardware-firmware quality and time-to-market.</li> </ul> Qualifications: <ul> <li>To be eligible, applicants must be pursuing a bachelor's degree in electrical engineering, Electrical Engineering Technology, Computer Science or related field or have completed their bachelor's degree within the last 12 months, regardless of age. </li> </ul> Preferred Additional Skills: <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Knowledge using Verilog for Logic Design.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Knowledge using SystemVerilog for verification with AVM, VMM, OVM, or UVM a plus</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Programming experience in C for embedded systems, including development of algorithms, manipulation of data structures, and implementing highly optimized code.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with lab tools: Logic Analyzers, oscilloscopes, JTAG/ICE debuggers and protocol analyzers.</li> </ul>

Associate, FPGA / ASIC Verification Engineer (Cincinnati, OH, US, 45245) @ L3Harris Technologies, Inc.

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