About this role
<p class="MsoNormal"><span style="font-size:14.0pt"><strong><em><span style="line-height:107%;font-family:Verdana, sans-serif;color:black">Job Title: <span style="font-size:14.0pt;line-height:107%;font-family:Arial, sans-serif">Senior Specialist, Electrical Engineer – FPGA Modem Development </span></span></em></strong></span></p> <p class="MsoNormal"><span style="font-size:14.0pt"><strong><em><span style="line-height:107%;font-family:Verdana, sans-serif;color:black">Job Code: 36890</span></em></strong></span></p> <p class="MsoNormal"><span style="font-size:14.0pt"><strong><em><span style="line-height:107%;font-family:Verdana, sans-serif">Job Location: </span>Rochester, NY </em></strong></span></p> <p class="MsoNormal"><span style="font-size:14.0pt"><strong><em><span style="line-height:107%;font-family:Verdana, sans-serif">Job Schedule: 9/80; Employees work 9 out of every 14 days – totaling 80 hours worked – and have every other Friday off </span></em></strong></span></p> <p class="MsoNormal"><span style="font-size:14.0pt"><strong><span style="line-height:107%;font-family:Verdana, sans-serif;color:black">Job Description:</span></strong></span></p> <p class="MsoNormal"><span style="font-size:14.0pt">L3harris is seeking signal processing focused digital design and verification engineers to support our development of tactical communication products. The candidate will function in an FPGA developer/verification role, working in a cross functional team environment to design, verify and test modem/signal processing-based FPGA firmware for radio communication systems. Successful candidates must have experience with RTL development using VHDL, as well as FPGA verification methodologies using SystemVerilog. Candidate will be required to analyze requirements, create FPGA specifications/development plans, create FPGA verification/test plans, code firmware designs in VHDL, code test benches in System Verilog, and verify designs meet requirements.</span></p> <p class="MsoNormal"><span style="font-size:14.0pt"><strong><span style="line-height:107%;font-family:Verdana, sans-serif;color:black">Essential Functions:</span></strong></span></p> <ul> <li class="MsoNormal" style="font-size:14.0pt"><span style="font-size:14.0pt">Ability to analyze system requirements and architect FPGA based processing solutions based on requirements the latest FPGA digital technology.</span></li> <li class="MsoNormal" style="font-size:14.0pt"><span style="font-size:14.0pt">Experience implementing complex modem and/or DSP circuits in programmable logic using FPGA devices. Equivalent experience in ASIC design is also applicable.</span></li> <li class="MsoNormal" style="font-size:14.0pt"><span style="font-size:14.0pt">Broad experience in embedded system design and solutions for communications systems.</span></li> <li class="MsoNormal" style="font-size:14.0pt"><span style="font-size:14.0pt">Architect, Implement, and verify complex algorithms in FPGAs and Software</span></li> <li class="MsoNormal" style="font-size:14.0pt"><span style="font-size:14.0pt">Perform detailed analysis including requirements analysis, use case scenarios, conceptual design, trade studies, test, operation, and maintenance of radio communications products.</span></li> <li class="MsoNormal" style="font-size:14.0pt"><span style="font-size:14.0pt">Work with cross functional teams as needed to define and refine design requirements and implement.</span></li> <li class="MsoNormal" style="font-size:14.0pt"><span style="font-size:14.0pt">Develop self-checking test benches for FPGA design verification and validation using SystemVerilog.</span></li> <li class="MsoNormal" style="font-size:14.0pt"><span style="font-size:14.0pt">Assist in the development of high-level and detailed verification test plans consistent with system requirements and specifications</span></li> <li class="MsoNormal" style="font-size:14.0pt"><span style="font-size:14.0pt">Prepare design and implementation reviews. Present technical briefings and status to internal and external customers. </span></li> <li class="MsoNormal" style="font-size:14.0pt"><span style="font-size:14.0pt">Ability to obtain a Secret Clearance</span></li> </ul> <p class="MsoNormal"><span style="font-size:14.0pt"><strong><span style="line-height:107%;font-family:Verdana, sans-serif;color:black">Qualifications:</span></strong></span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span>Bachelor’s Degree and minimum 7 years of prior relevant experience. Graduate Degree and a minimum of 9 years of prior related experience. In lieu of a degree, minimum of 13 years of prior related experiencein FPGA development.</span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span><span style="color:#212529">E</span>xperience developing and verifying FPGA/ASIC based embedded system solutions.</span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span><span style="color:#212529">E</span>xperience in FPGA/ASIC development using VHDL or Verilog</span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span><span style="color:#212529">E</span>xperience in FPGA/ASIC verification using SystemVerilog</span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span><span style="color:#212529">Experience with integrating FPGA firmware on hardware </span></span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span><span style="color:#212529">Experience with FPGA Vendor Specific FPGA Implementation tools (Vivado/Quartus/Libero)</span></span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span>Experience working in a Linux based development environment</span></p> <p class="MsoNormal"><span style="font-size:14.0pt"><strong><span style="line-height:107%;font-family:Verdana, sans-serif;color:black">Preferred Additional Skills:</span></strong></span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span>Experience with MatLab, Simulink or similar digital signal processing (DSP) modelling tools</span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span>Experience in communication system signal processing theory and waveform design</span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span>Experience with TCL or Python scripting languages</span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span><span style="color:#212529">Working knowledge and experience </span>in implementation and testing <span style="color:#212529">of MODEM RF Designs </span></span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span>Experience with Universal Verification Methodology (UVM)</span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span>Working knowledge and experience with vendor specific FPGA verification tools (Mentor Questa, Visualizer)</span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span><span style="line-height:107%;font-family:Verdana, sans-serif">Active US Government security clearance </span></span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span>Ability to work efficiently with remotely located teams and co-workers</span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span>Solid technical writing skills and ability to communicate technical concepts/solutions both inside and outside of the organization. </span></p> <p style="padding-left:40.0px"><span style="font-size:14.0pt"><span style="font-family:Symbol">·<span style="font-style:normal;font-weight:normal;line-height:normal;font-family:'Times New Roman'"> </span></span>Experience with Software Configuration Management (SCM) tools such as SVN (Subversion), GIT (Bitbucket), etc.</span></p> <p><span style="font-size:14.0pt">In compliance with pay transparency requirements, the salary range for this role in New York State is $92,500- $171,500. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements. </span></p> <p><span style="font-size:14.0pt">#LI-MA1</span></p>