Job Title: Lead, RF/Wireless Engrg Job Code: 39397 Job Location: Yorba Linda, California, On Site Job Schedule: 4/10: Employees work 10 hour days, 4 days a week with every Friday off Job Description: As a Lead Electrical Engineer, the candidate must have experience with L band RF systems, able to work from customer requirements to derive additional requirements, define the architecture of a possible solution based on requirements, setup a requirements schema & link requirements to documents (systems/subsystem specification, hardware/RF architecture description document, etc.) and flow down applicable requirements to other groups (software, ASIC, & test) so that they can contribute to realize the end solution based on the proposed architecture. The Lead EE will also oversee the development a qualification test plan that will ensure that the architecture and solution satisfy the customers’ requirements. The Lead EE will also work with subject matter experts in the areas of GPS signal processing, anti-jam signal processing, other hardware design team members, control software, and government qualification standards. As a Lead EE, the candidate is expected to understand each aspect of the technology used in the proposed solution. The Lead EE also must work with the cost account manager, program management, and project management to develop the solution within the program’s budget and schedule. Essential Functions: <ul style="margin-top:0.0in;margin-bottom:1.0 E-4pt"> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Requires comprehensive level knowledge of Electrical Engineering low frequency and high frequency (RF) Analog and Digital circuit design.</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Experience with RF systems, ideally GPS receivers</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Able to contribute to providing innovative Electrical Engineering solutions consistent with business development plans.</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Ability to develop circuit designs, requirements, design descriptions, verification plans/procedures, customer CDRLs to meet program schedules.</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Ability to support cross functional teams for cross functional conflict resolution, Root Cause Analysis, blank page architecture developments and design</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Ability to contribute to algorithm development, analysis, implementation, system architecture, verification, and Test with emphasis on military GPS electronics. </li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Ability to contribute to execution of design, build, integration and test activities, problem resolution and verifying that the deliverable products meet all program and customer requirements.</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Ability to provide project management reports as required, support senior level and customer reviews as necessary.</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Ability to provide inputs and reviews of the engineering technical baseline as part of proposal efforts.</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Ability to interface with the program’s leadership and other teams (SW, Systems, ME, and Test) on a frequent basis, conduct or participate in customer and/or program technical review presentations, and provide progress status updates on work products.</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Ability to participate or lead in the product development process including design reviews.</li> </ul> <ul style="margin-top:0.0in;margin-bottom:1.0 E-4pt"> <li style="margin:0.0in 53.45pt 1.0 E-4pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif">5 to 10% Travel required.</li> </ul> Qualifications: <ul style="margin-top:0.0in;margin-bottom:1.0 E-4pt"> <li style="margin:0.0in 53.45pt 1.0 E-4pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Bachelor’s Degree and a minimum of 9 years of prior relevant experience or Graduate Degree and a minimum of 7 years of prior related experience or in lieu of a degree, a minimum of 13 years of prior related experience.</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Minimum of 5 years’ experience in ability to capture schematics design and PCBA Layout using modern EE CAD such as Altium or Mentor Graphics. </li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif">5 years’ experience with project management and product design team leadership guided by individual annual goals and objectives with minimal oversight or direction; working in a team environment as an individual contributor. </li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif">6 years’ strong experience with receiver, Antenna, or Radio design (i.e. RF).</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif">4 years’ experience with embedded Hardware design.</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif">2 years’ experience with FPGA design with emphasis in digital signal processing (DSP)</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif">4 years’ experience demonstrating strong verbal and written skills</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif">7 Years experience with design tools such as MATLAB/Simulink, P-Spice, Agilent ADS (or AWR), Schematics Capturing/PCBA Layout tools such as Altium, and Ansys HFSS</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif">2 Years’ experience with FPGA design tools such as Xilinx ISE, Xilinx EDK, and ModelSim</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Must have ability to obtain a Secret Security Clearance.</li> </ul> <ul style="margin-top:0.0in;margin-bottom:1.0 E-4pt"> <li style="margin:0.0in 53.45pt 1.0 E-4pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Must be willing to travel 5 to 10% of time.</li> </ul> Preferred Additional Skills: <ul style="margin-top:0.0in;margin-bottom:1.0 E-4pt"> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Strong familiarity with GPS Module design and topology. </li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Advanced with High-speed Analog design methodologies. </li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Advanced in MS Office, design tools such as Simulink/MATLAB, P-Spice, Altium (Schematics Capturing & PCBA Layout), Agilent ADS (or AWR), and Ansys HFSS.</li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Familiar with FPGA design methodologies. </li> <li style="margin:0.0in 53.45pt 1.0 E-4pt 5.0px;font-size:11.0pt;font-family:Calibri, sans-serif">Proficient with DO-254 design</li> </ul> In compliance with pay transparency requirements, the salary range for this role in California, Massachusetts, New Jersey, Washington, and the Greater D.C, Denver, or NYC areas is MIN: $127,500.00 - MAX: $236,500.00. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements. #LI-KA1

Lead, RF/Wireless Engrg (Yorba Linda, CA, US, 92887) @ L3Harris Technologies, Inc.

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