About this role
<p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Title: Sr. Specialist, Electrical Engineer - FPGA</strong></span></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Code: 37019</strong></span></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Location: Palm Bay, FL</strong></span></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Schedule: 9/80- employees work 9 out of 14 days, totaling 80 hours worked-and have every other Friday off</strong><br><br></span></p> <p style="line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><span style="color:black">Job Description:</span></strong></span></p> <p style="line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">We are looking for a talented FPGA design engineer with industry experience in wireless digital communications, modems, networking, and/or digital signal processing (DSP). Designs, develops, verifies, and maintains FPGA and ASIC components in accordance with engineering, scientific and manufacturing requirements. Applies the appropriate standards, processes, procedures and tools throughout the product life cycle to support the development of new and sustainment of legacy products. May interface with customers, vendors, and other cross functional technical and support personnel.</span></p> <p style="line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">Areas of desired technical experience or education include:</span></p> <p style="text-indent:0.5in;line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">• Modulation</span></p> <p style="text-indent:0.5in;line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">• Demodulation</span></p> <p style="text-indent:0.5in;line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">• Digital filters</span></p> <p style="text-indent:0.5in;line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">• Forward Error Correction (FEC)</span></p> <p style="text-indent:0.5in;line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">• Networking</span></p> <p style="text-indent:0.5in;line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">• Industry standard interfaces (e.g. 10/100/1000 Ethernet, SPI, UART, SDRAM, DDR3, JESD, PCIe, Ethernet).</span></p> <p style="text-indent:0.5in;line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">• FPGA verification through simulation and unit testing.<br><br><br><br></span></p> <p style="line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><span style="color:black">Essential Functions:<br><br><br><br></span></strong></span></p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">Design, implement, and troubleshoot complex modem and/or DSP circuits in programmable logic using FPGA devices. </span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">Broad experience in signal processing for RF communications systems.</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">Design, implement, and verify FPGA and ASIC solutions</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">Participate in code reviews, design reviews, and integration activities</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">Support product integration and test activities in the lab and field as needed</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">Contribute to continuous improvement and innovation within the team</span></li> <li><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">Must have SECRET security clearance</span></span></li> </ul> <p style="line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><span style="color:black">Qualifications:</span></strong></span></p> <p style="line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">Bachelor’s Degree (preferably in Electrical Engineering, Computer Engineering, or a related field) and minimum 6 years of prior relevant experience. Graduate Degree and a minimum of 4 years of prior related experience. In lieu of a degree, minimum of 10 years of prior related experience.</span></li> </ul> <p style="line-height:normal;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;margin-left:0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"> </p> <p style="line-height:normal;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;margin-left:0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"> </p> <p style="line-height:normal;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;margin-left:0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"> </p> <p style="line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><span style="color:black">Preferred Additional Skills:<br><br><br><br></span></strong></span></p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif">Experience in communication system signal processing theory and waveform design</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">Working knowledge and experience in testing and debugging of Cryptographic Unit Designs</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">Experience with FPGA Vendor Specific FPGA Implementation tools (Vivado/Quartus)</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif">Experience in laboratory debug techniques using digital scopes, logic analyzers, BERTS, and other complex measurement devices.</span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">Knowledge of SATCOM architecture</span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">4 years of experience in FPGA / ASIC programming using VHDL</span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">4 years of experience with MatLab, Simulink or similar DSP modelling tools. Demonstrated ability to analyze and debug FPGA firmware and related hardware issues</span></li> </ul> <p><span style="color:white">#LI-JD3 </span></p>