Job Title: Manager, FPGA Engineer Job Code: 36360 Job Location: Bristol, PA Job Schedule: 9/80- employees work 9 out of 14 days, totaling 80 hours worked-and have every other Friday off Job Description: <div> <div> L3Harris Telemetry & RF Products is seeking a Manager, Digital Hardware Engineering to support the development of digital hardware solutions for its telemetry and data acquisition products. This is a hands-on leadership role that combines technical contribution with management of a cross-functional engineering team. </div> <div> The selected candidate will contribute to digital hardware and FPGA development while leading and mentoring engineers across Electrical and Software Engineering disciplines. </div> <div> Key Responsibilities </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Lead and support a team of engineers, including work assignment, performance management, coaching, and development planning. </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Provide day-to-day technical guidance and mentorship to engineers. </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Support staffing, employee development, and resource planning. </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Assist with project planning, proposal support, and status reporting. </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Contribute to the design and development of hardware for telemetry and data acquisition products. </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Support FPGA design, coding, simulation, integration, and test activities. </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Develop and review technical requirements, specifications, and design documentation. </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Support hardware integration, troubleshooting, and verification efforts. </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Collaborate with cross-functional teams across Electrical, Software, and related engineering disciplines. </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Lead efforts to improve and enhance engineering development processes, policies, and best practices to drive quality, consistency, and execution across the team. </li> </ul> </div> <div> Minimum Qualifications </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field and 9+ years of prior relevant experience; or graduate degree and 7+ years of related experience; or 13+ years of related experience in lieu of a degree. </li> </ul> </div> </div> <div> <div> Preferred Qualifications </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Strong communication, collaboration, and problem-solving skills. </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Experience leading small teams or serving in a functional leadership role. </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Experience with Xilinx, Altera, or Microchip FPGA tools and architectures. </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Experience with hardware integration, verification, and troubleshooting. </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Familiarity with telemetry, flight test, or other embedded hardware systems. </li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"> Minimum of 5 years of experience in digital hardware design, including circuit design and schematic capture. </li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Minimum of 5 years of experience in FPGA design and development, including experience with VHDL or similar hardware description languages. </li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Ability to obtain a U.S. Secret Clearance. </li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Minimum of 3 years of experience providing technical leadership, project guidance, or mentorship. <div> <div> </div> <div> </div> </div> <div> </div> </li> </ul> </div> </div> #LI-JD3

Manager, Field-Programmable Gate Array Engineer (Bristol, PA, US, 19007) @ L3Harris Technologies, Inc.

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