Job Title: Manager, Electrical Engineering (FPGA) Job Code: 38025 Job Location: Rochester, NY Job Schedule: 9/80 - Employees work 9 out of every 14 days – totaling 80 hours worked – and have every other Friday off OR 5/8: Employees work 8 hours per day, 5 days a week Job Description: L3harris is seeking an Electrical Engineering Manager with an FPGA/Digital Design background to support our development of secure tactical communication products. The Candidate will manage and lead a team of embedded FPGA engineers developing FPGA firmware for wireless communication system applications and products. Candidate must have 8+years experience in FPGA/Firmware development, as well as experience in technical team and project leadership. Candidate will be responsible for managing resources, schedule, and budget for firmware development projects. Candidate will work with cross functional teams to define, design, and verify FPGA solutions for radio product development projects. Candidate will be responsible for all supervisorial tasks and career development of direct reports. Essential Functions: <ul style="margin-bottom:12.4pt;margin-top:0.0px"> <li style="margin:0.0in 0.0in 12.4pt 0.0px;line-height:115%;font-size:11.0pt;font-family:Calibri, sans-serif">Management responsibilities for a team of FPGA engineers, including setting goals, timecard responsibilities, development plans, and training.</li> <li style="margin:0.0in 0.0in 12.4pt 0.0px;line-height:115%;font-size:11.0pt;font-family:Calibri, sans-serif">Responsible for driving teams work to delivery completion and metrics of the team.</li> <li style="margin:0.0in 0.0in 12.4pt 0.0px;line-height:115%;font-size:11.0pt;font-family:Calibri, sans-serif">Maintain and drive improvement of FPGA Development processes</li> <li style="margin:0.0in 0.0in 12.4pt 0.0px;line-height:115%;font-size:11.0pt;font-family:Calibri, sans-serif">Create FPGA development cost estimates and schedules</li> <li style="margin:0.0in 0.0in 12.4pt 0.0px;line-height:115%;font-size:11.0pt;font-family:Calibri, sans-serif">Manage budget and schedule of assigned development projects</li> <li style="margin:0.0in 0.0in 12.4pt 0.0px;line-height:115%;font-size:11.0pt;font-family:Calibri, sans-serif">Ability to Obtain a US Security Clearance.</li> </ul> Qualifications: <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-bottom:2.1pt;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">BS degree in Electrical or Computer Engineering discipline or another STEM Bachelor's Degree with a minimum of 8 years of relevant experience developing and verifying FPGA/ASIC based embedded system solutions.</li> </ul> <ul style="margin-bottom:2.1pt;margin-top:0.0px"> <li style="margin:0.0in 0.0in 2.1pt 0.0px;line-height:115%;font-size:11.0pt;font-family:Calibri, sans-serif">Demonstrated project leadership and management skills in embedded system and FPGA/ASIC design</li> <li style="margin:0.0in 0.0in 2.1pt 0.0px;line-height:115%;font-size:11.0pt;font-family:Calibri, sans-serif">Working knowledge of FPGA/ASIC development and verification processes.</li> </ul> Preferred Additional Skills: <ul style="margin-bottom:2.1pt;margin-top:0.0px"> <li style="margin:0.0in 0.0in 2.1pt 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Experience in VHDL/Verlilog coding for synthesis</li> <li style="margin:0.0in 0.0in 2.1pt 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Experience in FPGA/ASIC verification using SystemVerilog</li> <li style="margin:0.0in 0.0in 2.1pt 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Experience in UVM/OVM FPGA/ASIC verification methodology </li> <li style="margin:0.0in 0.0in 2.1pt 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Experience in development of embedded cryptographic security solutions for communciation products </li> <li style="margin:0.0in 0.0in 2.1pt 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Experience in development of signal processing solutions for communciation products </li> </ul> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-bottom:2.1pt;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Highly motivated, self-starter, who works well in team environments and is willing to lead and mentor others. </li> <li style="margin-bottom:2.1pt;margin-top:0.0in;margin-right:0.0in;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Solid technical writing skills and ability to communicate complex technical concepts/solutions both inside and outside of the organization.</li> </ul> <ul style="margin-bottom:10.0pt;margin-top:0.0px"> <li style="margin:0.0in 0.0in 10.0pt 0.0px;line-height:115%;font-size:11.0pt;font-family:Calibri, sans-serif">Ability to work efficiently with remotely located teams and co-workers </li> <li style="margin:0.0in 0.0in 8.0pt 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Active SECRET Clearance</li> </ul> In compliance with pay transparency requirements, the salary range for this role in New York state is $108,500 - $201,500. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements. #LI-MA1

Manager; Electrical Engineering (FPGA) (Rochester, NY, US, 14610) @ L3Harris Technologies, Inc.

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