Job Title: ASIC/FPGA Design Engineer (SMES) Job Code: 34234 Job Location: Camden, NJ Schedule: 9/80 Regular with every other Friday off Are you ready to take your engineering career to the next level and be a part of something truly extraordinary? Join our trailblazing team in the Philadelphia metro area, where you'll dive into the thrilling world of high-assurance encryption products and programs that are pivotal to national defense. Our rapidly expanding business is not just growing—it's exploding with opportunities for innovation and impact in network and tactical encryption products and systems. Imagine working on the front lines of technology, developing state-of-the-art solutions that safeguard our nation's security. You'll collaborate with some of the brightest minds in the industry, in an environment that champions creativity and excellence. If you're passionate about tackling complex challenges and eager to contribute to groundbreaking projects that make a real difference to our warfighters, citizens, and nation; this is your chance to shine. Apply now and embark on this exhilarating journey with us, shaping the future of defense technology! Eligible candidates with an active government issued clearance upon the time of hire will receive a sign-on payment in the amount of $ 15,000. Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols. L3Harris has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS). This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security. Essential Functions: <ul> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Responsible for deriving engineering specifications from system requirements and developing detailed architecture</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Generate test plans</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Silicon/FPGA bring up, characterization and production ramp/support/collateral</li> </ul> Qualifications: <ul> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">BSEE, MSEE Preferred.</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">5+ year’s equivalent experience developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Proficient with CDC, RDC. Formal EDA.</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Proficient in VHDL.</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Strong logic/board debug, and analytical skills.</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Experience with project leadership and EVM</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Excellent written, verbal, and presentation skills.</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Active SECRET Clearance</li> </ul> Preferred Additional Skills: <ul> <li class="MsoListParagraphCxSpMiddle" style="text-indent:-0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif"> A big plus if the candidate possesses “any” of the following: </li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:-0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif"> Proficiency in C++ (OOP)</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:-0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif"> Proficiency with Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:-0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif"> Knowledge of PCIe, NVMe, USB protocols.</li> <li class="MsoListParagraphCxSpMiddle" style="text-indent:-0.25in;line-height:107%;font-size:12.0pt;font-family:verdana, geneva, sans-serif"> Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto ).</li> </ul> In compliance with pay transparency requirements, the salary range for this role is $111,515 - $151,500. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements.

ASIC/FPGA Design Engineer (SMES) (Camden, NJ, US, 08103) @ L3Harris Technologies, Inc.

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