About this role
<p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><em>Job Title: </em></strong><strong><em>Specialist, Electrical Engineering (FPGA)</em></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><em>Job Code: </em></strong><strong><em>40150</em></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><em>Job Location: </em></strong><strong><em>Clifton, NJ</em></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><em>Job Schedule: 9/80: Employee works 9 out of every 14 days – totaling 80 hours worked – and have every other Friday off</em></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> <br><br><br></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Description:<br><br><br></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> </strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">L3Harris EW in Clifton, NJ has an immediate need for highly motivated FPGA design engineer. In this role you will develop, simulate, and integrate in lab highly specialized firmware designs targeting electronic warfare systems. Responsibilities include generation of firmware derived requirements, architecture of digital solutions to meet said requirements and formal test / lab verification of the functional system. The qualified candidate is able to work semi-autonomously as a lead designer, potentially driving a small team of firmware engineers through coding, simulation, code analysis, and circuit card design support.</span></p> <p><br><br></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Essential Functions:</strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> <br><br><br></strong></span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Decompose and allocate system and box-level requirements to FPGA specifications.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Architect solutions targeting FPGAs against requirements and implement those solutions on FPGA platforms.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Map FPGA simulation work products to system-level requirements and capabilities</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Review product specifications, and generate system and module-level block diagrams, flow diagrams, and design concepts</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Refine and enforce consistent firmware development processes across FPGA designs.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Support team leaders generating FPGA design solutions.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Ensure the FPGA simulations verify performance, then integrate and test the FPGA on the circuit card assembly.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Participate in the full life cycle development and integration of VHDL into different families of FPGAs.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience coding in VHDL and modeling algorithms, simulating and integrating multiple FPGA-based modules</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Drive the bench-level system integration with hardware, software, and other FPGA designs</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Support the planning and execution of project plans, design reviews and production release of modified or new product documentation</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Support qualification and production test in the event of test failures</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Candidate must be a U.S. citizen and be able to obtain a Security Clearance.</span></li> </ul> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> </strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> </strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> </strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> </strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Qualifications:</strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> <br><br><br></strong></span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">BS Degree in electrical/computer engineering and 4+ years of professional experience, an MS degree in electrical/computer engineering and 2+ years of professional experience, or 8+ years of related experience without a degree</span></li> </ul> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> <br><br><br></strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Preferred Additional Skills:</strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> <br><br><br></strong></span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">An active Secret security clearance</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Thorough understanding of version control best practices and tools (subversion, git, etc.) to closely track changes to the FPGA baseline.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with control protocols such I2C, SPI, RS-232/422, and DDR3 / DDR4.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with complex block and top-level simulations of FPGA designs requiring high level transaction-based models.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Ability to multi-task and prioritize assignments in a fast-paced work environment and to complete design/project goals with minimal oversight and direction.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Formal FPGA verification experience, UVM, Directed Testing, Code Coverage</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with and understanding of Altera or Xilinx FPGA architectures</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with high-speed serial protocols (PCI Express, SRIO, Ethernet)</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience designing Network Interface Designs</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience in network protocols including IPv6 and UDP</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with SoC (Kintex UltraScale/UltraScale+, Virtex UltraScale/UltraScale+, Zynq UltraScale)</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with VHDL</span></li> </ul> <p><br><br><br></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">In compliance with pay transparency requirements, the salary range for this role in New Jerseyis [$92,500 - $171,500 MAX]. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements. </span><br><br><span style="color:white;font-family:verdana, geneva, sans-serif;font-size:14.0pt">#LI-JD3 </span></p>