About this role
<p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Title: Scientist, Electrical Engineer (Digital Hardware Design)</strong><strong> </strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Code: </strong><strong>38126</strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Location: Salt Lake City, Utah</strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Schedule: 9/80- employees work 9 out of 14 days- totaling 80 hours worked- and have every other Friday off</strong></span></p> <p> </p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">L3Harris is seeking a motivated Senior Hardware Engineer to design and deliver advanced, mission-critical digital circuit technology for military communications systems, including software-defined radio applications.</span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">In this role, you will serve as a senior technical contributor, helping develop innovative digital hardware solutions for special operations and intelligence customers. You will work on complex national security challenges across areas such as threat deterrence, signals intelligence, cyber operations, machine learning, image processing, and data analytics. This position is part of a multidisciplinary team that values collaboration, innovation, and technical excellence.</span></p> <p> </p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Essential Functions</strong></span></p> <ul type="disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Provide hands-on technical expertise for digital hardware in communications systems programs.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Support the development of innovative electrical engineering solutions aligned with business objectives.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Develop circuit designs, requirements, design documentation, verification plans, procedures, and customer deliverables to meet program schedules.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Lead and support cross-functional teams in system architecture, design, root cause analysis, and issue resolution.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Design custom circuit card assemblies using FPGAs, embedded processors, networking components, and other electronics for challenging environmental conditions.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Apply knowledge of industry-standard interfaces such as 10GE, 40GE, 100GE, 10/100/1000BASE-T, SPI, UART, SDRAM, DDR3, DDR4, JESD, and PCIe.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Perform schematic capture, simulation, analysis, PCB layout, and hardware testing.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Contribute to algorithm development, implementation, system architecture, verification, and testing, with emphasis on military requirements.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Support proposal efforts through technical baseline reviews and engineering input.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Collaborate regularly with program leadership and cross-functional teams including software, systems, mechanical, and test engineering.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Participate in customer and program technical reviews and provide status updates on assigned work.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Travel up to 5% as required.</span></li> </ul> <p> </p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Qualifications</strong></span></p> <ul type="disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Bachelor’s degree in Computer Science, Computer Engineering, Software Engineering, or Electrical Engineering with 12 years of relevant experience; Graduate degree with 10 years of related experience. In lieu of a degree, 16 years of related experience.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Active DoD Secret Security Clearance.</span></li> </ul> <p> </p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Preferred Additional Skills</strong></span></p> <ul type="disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Strong foundation in communications theory and electronic warfare.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Ability to work independently or lead multidisciplinary teams in the development of communications systems and assemblies.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Minimum of 8 years of circuit card assembly (CCA) and hardware design experience.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Proficiency with Xilinx, Altera, or similar FPGA tools, and Siemens EDA (Mentor Graphics).</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with high-speed communications and I/O design, including networking and isolation requirements.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Hands-on experience with lab equipment such as oscilloscopes, logic analyzers, spectrum analyzers, receivers, signal generators, BERTs, TDR, and similar test equipment.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Knowledge of industry trends and emerging technologies, with the ability to support roadmaps that improve capability while reducing cost, size, weight, and power.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Minimum of 4 years of experience in hardware verification, schematic capture, and PCB layout.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Familiarity with version control tools such as Git or ClearCase.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Familiarity with product lifecycle management tools such as Teamcenter.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Familiarity with Confluence or similar collaboration tools.</span></li> </ul> <p><span style="color:white;font-family:verdana, geneva, sans-serif;font-size:14.0pt">#LI-CS3</span></p>