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Sr. Specialist, Electrical Engineer (FPGA Design) (Waterdown, ON, CA, L9H 0C5) @ L3Harris Technologies, Inc.

Waterdown, ON, CA, L9H 0C5OnsiteFull-time
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<p><span style="font-size:14.0pt"><span style="font-family:Verdana, Geneva, sans-serif"><strong>Job Title: Sr. Specialist, Electrical Engineer (FPGA Design)</strong></span></span></p> <p><span style="font-size:14.0pt"><span style="font-family:Verdana, Geneva, sans-serif"><strong>Job Code: 37915</strong></span></span></p> <p><span style="font-size:14.0pt"><span style="font-family:Verdana, Geneva, sans-serif"><strong>Job Location: Waterdown, Ontario</strong></span></span></p> <p><span style="font-size:14.0pt"><span style="font-family:Verdana, Geneva, sans-serif"><strong>Work Schedule: 9/80</strong></span></span></p> <p> </p> <p><span style="font-size:14.0pt"><span style="font-family:Verdana, Geneva, sans-serif"><strong>About L3HARRIS WESCAM </strong></span></span></p> <p><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">As a subsidiary of L3Harris Technologies and within the Communications &amp; Spectrum Dominance (CSD) Segment, the WESCAM division develops the most advanced optical sensor and targeting systems for global defense and military sectors, national security, search &amp; rescue and airborne law enforcement agencies. From long-range covert surveillance missions to search and rescue operations, our MX-series systems, and the mission systems solutions they are part of, produce stabilized high-magnification electro-optical and infrared images from airborne, marine and ground based platforms, enabling our customers to see first and act first.</span></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><strong><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:black">About the Role</span></strong></p> <p style="margin:0.0in;text-align:justify;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in 0.0in 6.0pt;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">We are a team full of bright and exceptionally friendly people who work together to create a wide variety of solutions to complex and challenging problems. In order to ensure exceptional results, our team creates reusable IP by following a rigorous process that begins with requirements, is supported by documentation and ends with verification. </span></p> <p style="margin:0.0in 0.0in 6.0pt;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Are you tired of critical customer bugs causing you to work every weekend? If so, you may be ready to trade some of your frustration for a process that has been proven to produce nearly perfect designs. Our team follows a standardized work flow and an efficient process that enables us to consistently create robust and reliable designs that our customers can rely upon. We focus our energy on future solutions, not fixing past mistakes.</span></p> <p style="margin:0.0in 0.0in 6.0pt;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Our team is split into two equally valuable groups. The Design team owns the design and is responsible for creating innovative solutions for our customers. The Verification team is committed to confirming that the modules we produce behave exactly as specified. Neither group could stand on its own, but together are successful. Our team of highly skilled individuals have both a depth and breadth in their roles. We all perform some level of verification; we all participate in requirements definition &amp; design engineering and we all take an active role in developing new design concepts and product launches.</span></p> <p style="margin:0.0in 0.0in 6.0pt;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">An FPGA design cannot live in isolation and we collaborate regularly with other departments to ensure the best solution at the system level. This collaboration has earned us a reputation for producing high quality designs that are easy to integrate and actively supported. We track and report design progress so that our Leadership team can be well informed as they allocate resources.</span></p> <p style="margin:0.0in 0.0in 6.0pt;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">We also understand the complex world of FPGA designs as a marathon, not a sprint. We recognize that being excellent in life goes well beyond engineering and includes actively participating in our communities and spending time with friends and family. With this in mind, we set aggressive but achievable goals that allow us to feel challenged while maintaining a work life balance.</span></p> <p style="margin:0.0in 0.0in 6.0pt;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">In short, it is a great place to work!</span></p> <p style="margin:0.0in;text-align:justify;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><strong><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:black">Primary Responsibilities </span></strong></p> <p style="line-height:normal;margin:0.0in 0.0in 8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">You will join the FPGA Design team and actively participate in the new product introduction (NPI) design process by creating solutions using digital design techniques primarily in the context of FPGA technology. This includes:</span></p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Creating FPGA designs using the VHDL language</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Simulating your designs using Questa Sim</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Utilizing Xilinx design tools for synthesis, implementation, debugging and timing closure</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Assisting the Verification Team as required</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Integrating library modules within a larger FPGA design</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Verifying, Testing and debugging in hardware</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Participating in regular design reviews</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Presenting FPGA status updates at regular NPI project meetings</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Supporting product sustaining operations</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Generating high quality documentation</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Following departmental practices and coding guidelines</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Providing input and support to others outside of the FPGA team</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Contributing to the team’s knowledge by sharing lessons learned</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Participate in company educational events and training as needed</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Propose ideas for, and participate in, continuous inter and intra-group innovation</span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Complete other tasks as assigned by Manager</span></li> </ul> <p style="margin:0.0in 0.0in 3.0pt 0.25in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">We are specifically looking for someone who is:</span></p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Passionate about being excellent, yet humble enough to learn from others</span></li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">A collaborator, knowing that it improves the results of independent work</span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Excited to follow a workflow and process that will produce high quality designs</span></li> </ul> <p style="line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif;margin:0.0in 0.0in 8.0pt 0.0px"> </p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="color:black"><strong><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">Required Education and Experiences</span></strong></span></p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Bachelor’s Degree in Electrical or Computer Engineering, or equivalent and minimum 6 years of prior relevant experience, or</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Graduate Degree and a minimum of 4 years of prior relevant experience, or</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">In lieu of a degree, minimum of 10 years of prior relevant experience.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Meets the requirements of the Canadian Controlled Goods Registration Program and is eligible for a Canadian government security clearance (required)</span></li> </ul> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><strong><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:black">Desired Skills and Capabilities </span></strong></p> <ul> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Knowledge of Digital Signal Processing techniques</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Experience with Digital or Analog Video</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040">Matlab for algorithm development</span></li> <li style="line-height:normal;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#404040"><span style="line-height:107%;color:#404040">Experience with DO254 or other standardized safety critical processes</span> </span></li> </ul> <p style="line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">This posting is for a current vacancy. In the province of Ontario, Canada, the pay range for this position will be $102,000 to $152,000 </span></p> <p style="line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif">#LI-MA1</span></p>

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