About this role
<p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Title:</strong> <strong>Senior Associate, Hardware Engineering, Tactical Data Links (TDL)</strong></span><br><strong><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Job Code: 37783</span></strong><br><strong><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Job Location: Carlsbad, California</span></strong><br><strong><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Schedule: 9/80 (employee's work 9 out of every 14 days - totaling 80 hours worked - and have every other Friday off)</span></strong></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> </strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Description:</strong></span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">The <strong>Hardware Engineering</strong> and <strong>Development team</strong> is product focused and sees their <strong>designs from initial concept</strong> to <strong>development</strong> and <strong>through production</strong>. Candidates will work closely with Systems and Software Engineering, CAD, Components Engineering, and Manufacturing teams to <strong>ensure designs meet all requirements</strong> and <strong>are producible</strong>. </span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">As a <strong>Hardware Engineer</strong> <strong>supporting</strong> the <strong>Tactical Data Links line of business</strong> within our Spectrum Superiority Segment, you'll have the opportunity to:</span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Participate in <strong>system requirements definition</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Lead</strong> and participate in <strong>high-level design</strong> and <strong>low-level design review</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Produce and <strong>test design deliverables</strong> such as <strong>Circuit Card Assemblies</strong> in <strong>RF</strong>, <strong>Digital</strong>, and <strong>mixed signal applications</strong></span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Create Bill of Materials</strong> and work with Planning and Supply Chain for part procurement</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Work closely with Component Engineering for <strong>part creation on new designs</strong> and sustaining current products</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Produce program deliverables and develop design-level documentation</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Ability to obtain a United States Secret Clearance</span></li> </ul> <p> </p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><u>Required Qualifications (one of the following):</u></strong></span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Degree and a minimum of 2 years of prior related experience.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Graduate Degree or equivalent with 0 to 2 years of prior related experience.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">In lieu of a degree, minimum of 6 years of prior related experience.</span></li> </ul> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> </strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><u>Preferred Additional Skills:</u></strong></span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">2 years of experience with design tools and processes for Schematic Capture, CAD, SPICE, ADS, Hyperlynx, MATLAB, AMD/Xilinx Vivado, Intel Quartus, and/or Modelsim/Questa</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Knowledge and/or experience with VHDL, Verilog, Power, Analog, Antennas, Controls, RF, Modem, EDA, DSP, MATLAB, Communication Systems, Aerospace industry</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Work and/or project experience in any of the following: Digital, Analog, or RF circuit design, Communications, Digital Signal Processing, Programmable Logic</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Excellent communication, technical writing, and presentation skills</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Excellent organizational skills with the ability to manage multiple projects and deadlines</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Familiarity with various computing environments (LINUX/Windows)</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Strong background in Digital, RF, Analog circuit design principles, DSP, Programmable Logic, and/or FPGAs</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Self-starter, collaborative, and independent</span></li> </ul> <p> </p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">In compliance with pay transparency requirements, the salary range for this role in California is $80,500 – $149,500. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements.</span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt;color:white">#LI-CD1</span></p>