About this role
<p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Title: Senior Specialist, Systems Test Engineer</strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job code: 39707</strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Location: Carlsbad, CA</strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Schedule: 9/80- employees work 9 out of 14 days- totaling 80 hours worked- and have every other Friday off</strong></span></p> <p> </p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>L3Harris’ Communication Systems segment is currently seeking a Senior Specialist, Systems Test Engineer – Electromagnetic Compatibility-Features (EMC-F) to join our team.</strong> This position will be based at our Carlsbad, CA facility.</span></p> <p> </p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Position Overview:</strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">The Senior Specialist, Systems Test Engineer – EMC-F will support system-level integration, verification, troubleshooting, qualification, and compliance-related activities for complex electronic and communications systems across the product lifecycle. This role is focused on EMC-Features and applies systems/test engineering rigor to requirements interpretation, verification planning, test readiness, issue investigation, and technical execution. The position works across cross-functional teams to identify and resolve integration issues, reduce technical risk, and support program milestones and customer commitments.</span></p> <p> </p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Essential Responsibilities:</strong></span></p> <ul type="disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Support system integration, verification, troubleshooting, qualification, production, and sustainment activities across multiple programs.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Interpret customer, system, and derived requirements and help translate them into executable verification and test approaches.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Develop and maintain verification plans, test procedures, compliance matrices, test reports, and supporting technical documentation.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Coordinate and support laboratory, subsystem, and system-level test activities including pre-test planning, execution support, data review, and post-test issue resolution.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Investigate and resolve technical issues encountered during design, integration, test, and qualification activities.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Work closely with cross-functional engineering teams to identify and mitigate risks related to system integration, interference, grounding, shielding, cabling, packaging, and other hardware implementation considerations.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Support EMC-Features related analysis, planning, test preparation, and issue resolution activities across the product lifecycle.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Interface with internal and external test organizations, suppliers, manufacturing, and customers regarding technical readiness, results, discrepancies, and corrective actions.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Provide technical input to design reviews, risk assessments, root-cause investigations, corrective actions, and program planning efforts.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Execute complex assignments with general oversight while balancing multiple concurrent priorities.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Mentor less experienced engineers and contribute to standard work, process improvement, and technical rigor across the team.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Ability to obtain and maintain a U.S. security clearance.</span></li> </ul> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> </strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Qualifications:</strong></span></p> <ul type="disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Bachelor’s Degree in Electrical Engineering, Systems Engineering, Physics, or a related technical discipline and a minimum of <strong>6 years of prior relevant experience</strong>, or Graduate Degree and a minimum of <strong>4 years of prior related experience</strong>. In lieu of a degree, minimum of <strong>10 years of prior related experience</strong>.</span></li> </ul> <p> </p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Preferred Qualifications:</strong></span></p> <ul type="disc"> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Bachelor’s or Master’s Degree in Electrical Engineering with coursework or concentration in electromagnetics, RF, signal integrity, or a related field.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience supporting system test, integration, verification, qualification, production, or sustainment activities for complex electronic, electrical, or communications systems.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience interpreting requirements and developing verification plans, test approaches, procedures, and reports.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience troubleshooting hardware, subsystem, or system-level technical issues in a multidisciplinary engineering environment.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience generating clear technical documentation such as test plans, procedures, reports, compliance matrices, discrepancy reports, or corrective action documentation.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience coordinating across cross-functional teams including design, test, manufacturing, suppliers, and customers.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Demonstrated ability to work independently on complex assignments with general oversight and manage multiple concurrent efforts.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Strong written, verbal, and interpersonal communication skills.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience supporting electromagnetic compatibility-related system integration, compliance, and qualification activities.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Familiarity with EMC-F principles, mitigation methods, and design considerations such as grounding, bonding, shielding, filtering, cabling, and installation practices.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with military, aerospace, avionics, telecom, medical device, or other regulated product development environments.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience supporting standards-based qualification or compliance testing.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with system-level integration and verification of complex electronic or communications hardware.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience analyzing technical failures, performing root-cause investigations, and developing corrective actions.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Familiarity with RF, signal integrity, packaging, or related electrical system behaviors that can affect integration and compliance performance.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience working with external laboratories, platform integrators, suppliers, or customers on technical compliance matters.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Ability to identify technical risk early and recommend practical corrective actions.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience mentoring junior engineers or influencing teams without direct authority.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Active U.S. security clearance.</span></li> </ul> <p><span style="color:white;font-family:verdana, geneva, sans-serif;font-size:14.0pt">#LI-CS3</span></p>