About ST Engineering ST Engineering is a global technology, defence, and engineering group with offices across Asia, Europe, the Middle East, and the U.S., serving customers in more than 100 countries. The Group uses technology and innovation to solve real-world problems and improve lives through its diverse portfolio of businesses across the aerospace, smart city, defence, and public security segments. Headquartered in Singapore, ST Engineering ranks among the largest companies listed on the Singapore Exchange. Our history spans more than 50 years, and our strategy is underpinned by our core values – Integrity, Value Creation, Courage, Commitment and Compassion. These 5 core values guide every aspect of our business and are embedded in our ST Engineering culture – from the people we hire, to working with each other, to our partners and customers. About our Business – Advanced Networks & Sensors Our Advanced Networks & Sensors business specializes in platform digitalization, advanced connectivity, and cutting-edge manufacturing. This diversity of capabilities presents a range of roles through which you can contribute to the development of innovative, secure, and patented products. Join our team and play a crucial role in developing tomorrow’s technology and connectivity solutions and services to sectors spanning defence, public security, government, and the commercial realm. Your work will have a global impact as we empower customers through advanced communications, intelligent sensors, and the deployment of AI-enabled Edge applications for mission-critical roles. Together, We Can Make A Significant Impact As a Senior / FPGA Engineer for Software Defined Radio (Baseband), you will be responsible to architect, implement, and validate baseband signal processing pipelines on modern FPGAs, integrating with high-speed ADC/DACs and RF front-ends. You will own the end-to-end flow—from algorithm prototyping to RTL implementation, timing closure, hardware-in-the-loop (HIL) validation, and production readiness. You will work on RF, embedded software, systems, and test engineering to deliver robust, scalable, and high performance SDR products. Be Part of Our Success Architecture & Design <ul> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Define SDR baseband architectures (DDC/DUC, filtering, FFT/IFFT, OFDM, MIMO/beamforming, automatic gain control, synchronization, timing/phase tracking).</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Partition algorithms across FPGA fabric, DSP blocks, and embedded CPU (SoC) for performance/latency/power trade-offs.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Develop high-speed I/O subsystems (e.g., JESD204B/C, PCIe, 10/25/100GbE, Aurora, AXI4).</li> </ul> Implementation & Verification <ul> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Implement DSP and control logic in VHDL/Verilog/System Verilog; leverage Vendor IP and HLS where appropriate.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Perform timing closure (setup/hold, CDC, multi-clock design), resource/power optimization, and floor planning.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Build test benches, UVM/lightweight verification, and hardware-in-the-loop tests with real RF signals.</li> </ul> Modeling & Prototyping <ul> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Prototype algorithms in MATLAB/Simulink or Python (NumPy/SciPy); ensure fixed-point accuracy and bit true correlation with RTL.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Develop golden reference models and maintain test vectors for continuous verification.</li> </ul> Integration <ul> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Interface with RF front-end (mixers, LNAs, filters) and high-speed converters (ADC/DAC), including clocking, PLLs, and synchronization.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Collaborate with firmware/software teams on drivers, DMA, kernel modules (Linux), and data path APIs.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Integrate with SDR frameworks (e.g., GNU Radio, custom pipelines) and external control planes.</li> </ul> Validation & Production Readiness <ul> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Execute lab bring-up using spectrum analyzers, VNAs, logic analyzers, and oscilloscopes.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Conduct EVM, BER, throughput/latency, spur/noise, and phase-noise/jitter characterization.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Support DFx (DFT/DFM), manufacturing test, and field diagnostics; contribute to compliance (EMC/EMI) planning.</li> </ul> Process & Documentation <ul> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Maintain requirements, interface specs, state machines, test plans, and design reviews.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Adopt Continuous Integration/Continuous Deployment practice workflow for FPGA builds, regression tests, and continuous integration.</li> </ul> Qualities We Value <ul> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Knowledge in Electrical Engineering, Communications Engineering, Computer Engineering, or related field.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">3–7 years of experience in digital communications, DSP, or baseband algorithm development (drone/telemetry experience preferred).</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Experience with embedded systems and real-time signal processing.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Hands-on exposure to FPGA/DSP hardware platforms and RF lab test equipment.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Strong knowledge of digital modulation/demodulation schemes (FSK, QPSK, QAM, OFDM, etc.).</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Proficiency in forward error correction (FEC) methods (convolutional codes, RS, LDPC).</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Expertise in digital filter design (FIR, IIR, adaptive filtering, equalization).</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Skilled in DSP implementation on FPGA/DSP/embedded platforms (e.g., Xilinx, TI DSPs).</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Proficiency with MATLAB, Simulink, Python, C/C++ for simulation and implementation.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Familiarity with RF test equipment (spectrum analyzers, VSAs, oscilloscopes).</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Willingness to participate in field trials and real-world testing under varying RF conditions.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Singaporean only</li> </ul> Our Commitment That Goes Beyond the Norm <ul> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">An environment where you will be working on cutting-edge technologies and architectures.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Safe space where diverse perspectives are valued, and everyone’s unique contributions are celebrated. </li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Meaningful work and projects that make a difference in people’s lives.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">A fun, passionate and collaborative workplace.</li> <li style="text-align:justify;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Competitive remuneration and comprehensive benefits.</li> </ul> Working Location: Jurong East

Senior / FPGA Engineer (ST Engineering Jurong East Bui, SG) @ ST Engineering

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