About this role
<div><span style="font-size:14.0px"><span style="font-family:arial, helvetica, sans-serif"><strong>Division:</strong> Mobile Solutions</span></span> </div> <div><span style="font-size:14.0px"><span style="font-family:arial, helvetica, sans-serif"><strong>Employment Status:</strong> Exempt</span></span></div> <div><span style="font-size:14.0px"><span style="font-family:arial, helvetica, sans-serif"><strong>Salary Grade:</strong> 108</span></span></div> <div><span style="font-size:14.0px"><span style="font-family:arial, helvetica, sans-serif"><strong>Shift: </strong></span></span></div> <div><span style="font-size:14.0px"><span style="font-family:arial, helvetica, sans-serif"><strong>Requisition ID:</strong> 77686 </span></span></div> <div><span style="font-size:14.0px"><span style="font-family:arial, helvetica, sans-serif"><span style="color:#000000"><em>Please be aware that if you are selected to formally interview for an internal position you will be required to notify your current manager. Please refer to the Employee Transfers Guidelines posted on Skylink.</em></span></span></span></div> <div> </div><div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Job Description</b></H2> </div><div><p style="margin:6.0pt 0.0in;text-align:justify;font-size:11.0pt;font-family:Calibri, sans-serif"><strong><u><span style="font-size:10.0pt;font-family:Arial, sans-serif;color:#002060">Job Description:</span></u></strong></p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 0.0px;text-align:justify;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Seeking a Principal Layout Designer responsible for the layout of Analog integrated circuits, utilizing commercial/standard bulk CMOS and SOI technologies in accordance with design rules.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;text-align:justify;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">In this role you will be working closely with design engineers in the layout and verification of analog and integrated circuits for wireless consumer electronic products using the Cadence Design environment and Calibre verification tools. </span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;text-align:justify;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Designer will participate in all aspects of project management, including, project planning, working with engineers to identify scope of project, validating designs, deliverables, and creation of manufacturing and assembly documentation within the required cycle time per company and program requirements. </span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;text-align:justify;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Position requires remote interfacing with domestic and international design engineering and layout teams in multiple design centers across multiple time zones. </span></li> </ul></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Responsibilities</b></H2> </div><div><ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="color:#3c3c3c;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Completes work through use of CAD layout software</span></li> <li style="color:#3c3c3c;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Works closely with the engineer to provide high quality layout in a timely manner</span></li> <li style="color:#3c3c3c;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Ability to do block level, macro level and top level; floor planning, assembly and verification</span></li> <li style="color:#3c3c3c;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Experience working in multiple processes</span></li> <li style="color:#3c3c3c;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Ability to lead peers/teams on complex blocks and top level</span></li> <li style="color:#3c3c3c;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Communicates regular status updates</span></li> <li style="color:#3c3c3c;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Takes on mentoring/leadership roles to promote high quality work of entire team</span></li> <li style="color:#3c3c3c;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Ability to learn and evaluate new tool/features with little supervision and proactively share knowledge with peers</span></li> <li style="color:#3c3c3c;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Ability to recognize common analog structures and floorplan blocks/”top level” utilizing best analog layout practices</span></li> <li style="color:#3c3c3c;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Create and give presentations, write “how to” documents and training instructions for layout and engineering peers.</span></li> <li style="color:#3c3c3c;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Recommends new/changes to policies, methodologies and established procedures </span></li> <li style="color:#3c3c3c;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Other duties as required.</span></li> </ul></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Qualifications</b></H2> </div><div><ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="color:#3c3c3c;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Bachelor’s degree in electrical engineering or equivalent</span></li> <li style="color:#3c3c3c;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif">Minimum 6+ years of experience in the layout of integrated circuits </span></li> </ul> <p style="margin:0.0in 0.0in 0.0in 0.25in;font-size:11.0pt;font-family:Calibri, sans-serif"><strong><span style="font-size:10.0pt;font-family:Arial, sans-serif;color:#002060">KNOWLEDGE, SKILLS, ABILITIES</span></strong></p> <p style="margin:0.0in 0.0in 0.0in 0.25in;font-size:11.0pt;font-family:Calibri, sans-serif"><strong><u><span style="font-size:10.0pt;font-family:Arial, sans-serif;color:#002060"> </span></u></strong></p> <p style="margin:0.0in 0.0in 0.0in 0.25in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif;color:#3c3c3c;background-color:white">Strong understanding of basic electrical properties and principles</span><span style="font-size:10.0pt;font-family:Arial, sans-serif;color:#3c3c3c"><br><span style="background-color:white">Strong familiarity with Cadence Virtuoso, Layout XL, SKILLCAD, Calibre and Unix</span></span></p> <p style="margin:0.0in 0.0in 0.0in 0.25in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif;color:#3c3c3c;background-color:white">Intermediate to advance knowledge on skill programming / writing scripts a plus</span><span style="font-size:10.0pt;font-family:Arial, sans-serif;color:#3c3c3c"><br><span style="background-color:white">Advanced knowledge of layout dependent effects with regarding to device and process matching techniques</span><br><span style="background-color:white">Execution in Top Level assembly of Layout</span><br><span style="background-color:white">Strong knowledge of Latch-up prevention</span><br><span style="background-color:white">Strong knowledge of ESD protection schemes</span><br><span style="background-color:white">Strong familiarity with P&R methods is a plus</span><br><span style="background-color:white">Outstanding communication and verbal presentation skills</span></span></p> <p style="background-color:white;margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:Arial, sans-serif;color:#3c3c3c"> Previous experience in the preparation of layout data for release to foundry a plus</span></p></div></div></div><p>Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.</p>