About this role
<div><span style="font-size:14.0px"><span style="font-family:arial, helvetica, sans-serif"><strong>Division:</strong> RMI Engineering</span></span> </div> <div><span style="font-size:14.0px"><span style="font-family:arial, helvetica, sans-serif"><strong>Employment Status:</strong> Exempt</span></span></div> <div><span style="font-size:14.0px"><span style="font-family:arial, helvetica, sans-serif"><strong>Salary Grade:</strong> 111</span></span></div> <div><span style="font-size:14.0px"><span style="font-family:arial, helvetica, sans-serif"><strong>Shift: </strong></span></span></div> <div><span style="font-size:14.0px"><span style="font-family:arial, helvetica, sans-serif"><strong>Requisition ID:</strong> 77301 </span></span></div> <div><span style="font-size:14.0px"><span style="font-family:arial, helvetica, sans-serif"><span style="color:#000000"><em>Please be aware that if you are selected to formally interview for an internal position you will be required to notify your current manager. Please refer to the Employee Transfers Guidelines posted on Skylink.</em></span></span></span></div> <div> </div><div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>About the role</b></H2> </div><div><p style="line-height:15.0pt;margin:0.0in;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-size:11.0pt;color:black">We are seeking an experienced Engineering Manager 2 to lead a multidisciplinary team spanning IC design, functional verification, and silicon validation. This role will drive end-to-end execution of complex SoC/ASIC programs, ensuring high-quality silicon delivery, first-pass success, and alignment with business objectives. The ideal candidate combines deep technical expertise with strong leadership, execution discipline, and a proven track record of delivering high-performance silicon products.</span></p></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Responsibilities</b></H2> </div><div><div> <p><strong>Technical Leadership</strong><br>Own end-to-end IC/SoC development from architecture through digital design, verification, tape-out, and post-silicon validation. Define and drive cross-functional methodologies, verification strategies, and validation frameworks. Ensure microarchitecture aligns with system requirements, PPA (performance, power, area), and product goals. Oversee coverage closure, design quality, and silicon readiness through customer sampling.</p> <p><strong>Execution & Delivery</strong><br>Manage multiple concurrent tape-outs with a focus on predictable, on-time delivery. Drive first-pass silicon success through robust verification and validation strategies. Handle technical risks, debug complexity, and schedule trade-offs effectively. Oversee silicon bring-up, debug, and production ramp.</p> <p><strong>Team Leadership</strong><br>Lead and scale teams across digital design, verification, and validation. Mentor both junior engineers and senior technical leaders, fostering development of next-generation talent. Build a high-performance culture centered on accountability, quality, and innovation. Own hiring, workforce planning, and performance management.</p> <p><strong>Cross-Functional Collaboration</strong><br>Partner with architecture, IC design, firmware, software, systems, and product management teams to ensure alignment. Collaborate closely with test, physical design, and manufacturing teams to achieve successful tape-outs. Engage with customers and external partners for technical alignment and issue resolution.</p> <p><strong>Process & Innovation</strong><br>Establish best-in-class design, verification, and validation flows. Drive automation across AI, CI/CD, regression, and debug analytics to improve productivity and efficiency. Evaluate and implement new tools, methodologies, and emulation/prototyping platforms. Promote adoption of AI/ML-driven verification and debug techniques.</p> <p> </p> <p><span>#LI-CB1</span></p> </div></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Required Experience and Skills</b></H2> </div><div><ul style="margin-bottom:0.0in;margin-top:0.0px" type="disc"> <li style="color:black;line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-size:11.0pt">Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field (PhD preferred)</span></li> <li style="color:black;line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-size:11.0pt">15+ years of experience in IC/SoC development with strong background in IC design, verification, and validation</span></li> <li style="color:black;line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-size:11.0pt">5+ years of experience in engineering leadership or management roles</span></li> <li style="color:black;line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-size:11.0pt">Proven track record of delivering complex SoCs through full lifecycle (architecture → silicon → production)</span></li> <li style="color:black;line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-size:11.0pt">Deep expertise in SystemVerilog/Verilog, UVM-based verification, and silicon validation</span></li> <li style="color:black;line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-size:11.0pt">Strong understanding of SoC architectures, buses (AXI/AHB/APB), and industry protocols (PCIe, DDR, Ethernet, etc.)</span></li> </ul></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Desired Experience and Skills</b></H2> </div><div><ul style="margin-bottom:0.0in;margin-top:0.0px" type="disc"> <li style="color:black;line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-size:11.0pt">Hands-on experience with emulation (Palladium, Veloce) and FPGA prototyping</span></li> <li style="color:black;line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-size:11.0pt">Expertise in formal verification and low-power design techniques</span></li> <li style="color:black;line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-size:11.0pt">Experience working with geographically distributed teams</span></li> <li style="color:black;line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-size:11.0pt">Experience in domains such as AI/ML accelerators, networking, or high-performance computing</span></li> </ul></div></div></div><p>Referral Bonus Program Reward (if eligible): Rs200,000.00 </p>