About this role
<p>If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. Through our broad technology expertise and one of the most extensive product portfolios in the industry, we are Connecting Everyone and Everything, All the Time.</p> <p> </p> <p>At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management, and the freedom to make meaningful contributions in a setting that encourages creative thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together are changing the way the world communicates.</p> <p>Requisition ID: 77738 </p><div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Description</b></H2> </div><div><p><span style="font-family:verdana, geneva, sans-serif">This position is for an experienced digital design engineer working our next generation wireless audio ASICs.</span></p></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Responsibilities</b></H2> </div><div><p><span style="font-family:verdana, geneva, sans-serif">You will architect, design and collaborate on radio subsystems in small geometry mixed-signal CMOS SOCs. Your primary role will be as a contributor to architecture and design in digital, including:</span></p> <ul> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Full chip/block level architecture, RTL design and implementation</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Emulation, modeling, simulation, silicon testing and debugging of digital circuits and SOCs</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Providing technical leadership and expertise in all aspects of digital design and implementation</span></li> </ul> <p><span style="font-family:verdana, geneva, sans-serif">You will work closely with your counterparts in analog, RF, firmware, test and evaluation teams to design and ensure functional and performance requirements are met by the subsystem. Your expertise in low power SOC design, signal processing, processor cores and ASIC implementation will make you a key member of the design group.</span></p></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Required Experience and Skills</b></H2> </div><div><p><span style="font-family:verdana, geneva, sans-serif">Proven track record of exceptional performance in digital design</span></p> <ul> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">5+ years (BSEE), 3+ years (MSEE) or 0+ years (PhD) of relevant industry experience</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Experience in implementation with Verilog and System Verilog</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Experience authoring specifications</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Experience in architectural modeling in Matlab, Python, or C</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Experience in Real-time data processing systems</span></li> </ul></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Desired Experience and Skills</b></H2> </div><div><ul> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Understanding of ASIC design flow (RTL design, Verficiation, Synthesis, Timing Analysis, Power Analysis, Physical Design, Test)</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Famililarity with wireless communication</span> <ul> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Different modulation schemes such as pi/4 DQPSK, 16QAM, GFSK</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Implementation of FIR/IIR filters</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Compensation for impairments such as Carrier Frequency Offset, Symbol Timing Recovery, Channel Equalization</span></li> </ul> </li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">ASIC prototyping using FPGA</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Embedded Firmware development using C (for testcase development and firmware debug)</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Lab evaluation using oscilloscopes, logic analyzers, spectrum analyzers</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Familiarity with Audio performance measurements (SNR, THD, SINAD, DR, etc.)</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Familiarity with external communication interfaces (SPI, I2C, I2S, UART, JTAG, etc.) </span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Familiarity with different processors (ARM, RISC-V)</span><br> <ul> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Familiarity interfacing to standard bus protocols such as AHB, APB, AXI</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Direct Memory Access controllers</span></li> </ul> </li> </ul> <ul> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Clock Domain Crossing techniques</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Low power design techniques</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Design For Test concepts</span></li> <li style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">Skilled in various scripting languages such as python, perl, TCL, Makefiles, shell scripts</span></li> </ul> <p style="font-family:verdana, geneva, sans-serif"> </p> <p style="font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif">#LI-SJ1</span></p></div></div></div><p>The typical base pay range for this role across the U.S. is currently USD $91,200 - $177,200 per year. Starting base pay will depend on relevant experience and skills, training and education, business needs, market demands, the ultimate job duties and requirements, and work location. Skyworks has different base pay ranges for different work locations in the U.S. Benefits include access to healthcare benefits (including a premium-free medical plan option), a 401(k) plan and company match, an employee stock purchase plan, paid time off (including vacation, sick/wellness, parental leave), among others. Employees are eligible to participate in an incentive plan, and certain roles are also eligible for additional awards, including recognition and stock. These incentives and awards are based on individual and/or company performance. </p> <p> </p> <p>Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law. Skyworks strives to create an accessible workplace; if you need an accommodation due to a disability, please contact us at [email protected].</p>