We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, <a href="http://www.teradyne.com/">Teradyne</a> companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learning something new every day. We cultivate a culture of inclusion for all employees that respect their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview Teradyne’s Semiconductor Test Division in Costa Rica seeks an enthusiastic candidate for the role of Semiconductor Design Engineer. As part of this position, you will be responsible for ensuring the robustness and efficiency of custom digital libraries and verifying timing constraints using Cadence tools. Your expertise in library development and timing analysis will be instrumental in achieving high-quality designs and ensuring reliable chip performance. Responsibilities <ul style="margin-bottom:0.0in;margin-top:0.0px" type="disc"> <li style="color:#343434;line-height:normal;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:10.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Develop detailed circuit specifications for mixed-signal circuits.</li> <li style="color:#343434;line-height:normal;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:10.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Design circuit architectures and transistor-level topologies to meet performance requirements.</li> <li style="color:#343434;line-height:normal;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:10.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Provide guidance for physical implementation (layout) of high-speed circuits.</li> <li style="color:#343434;line-height:normal;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:10.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Optimize circuits via simulation (using Cadence EDA tools) across various process and operating conditions.</li> <li style="color:#343434;line-height:normal;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:10.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Collaborate with library development teams to create and enhance digital libraries for standard cells and other custom components.</li> <li style="color:#343434;line-height:normal;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:10.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Characterize timing constraints, including setup and hold times, across various design modes using Liberate (corner cases, process variations, etc.).</li> <li style="color:#343434;line-height:normal;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:10.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Optimize library elements such as cell layouts, characterization, and timing models.</li> <li style="color:#343434;line-height:normal;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:10.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Perform static timing analysis (STA) using Cadence tools (such as Innovus, Tempus, Encounter and Liberate).</li> <li style="color:#343434;line-height:normal;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:10.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Debug and resolve timing violations, ensuring adherence to design specifications.</li> <li style="color:#343434;line-height:normal;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:10.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Work closely with physical design teams to ensure library integration and compatibility.</li> <li style="color:#343434;line-height:normal;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:10.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Develop and maintain library documentation, including timing models and guidelines.</li> <li style="color:#343434;line-height:normal;background-color:white;margin-top:0.0in;margin-right:0.0in;margin-bottom:10.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Participate in library quality assurance efforts and contribute to process improvements.</li> </ul> All About You We seek individuals who share our passion for precision, quality, and continuous improvement. Our commitment to customer success drives us to go the extra mile. Minimum Requirements <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 0.4px;line-height:normal;background-color:white;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">BS degree in electrical engineering or related field.</li> <li style="margin:0.0in 0.0in 0.0in 0.4px;line-height:normal;background-color:white;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">8 years of experience in: <ul> <li style="list-style-type:none"> <ul> <li style="list-style-type:none"> <ul style="list-style-type:square;margin-top:0.0in;margin-bottom:0.0in"> <li style="margin:0.0in 0.0in 0.0in 2.0px;line-height:normal;background-color:white;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">Designing and characterizing high-frequency, highly integrated mixed-signal integrated circuits.</li> <li style="line-height:normal;background-color:white;margin:0.0in 0.0in 0.0in 2.0px;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">All phases of multiple IC developments, from specification to product introduction.</li> <li style="line-height:normal;background-color:white;margin:0.0in 0.0in 0.0in 2.0px;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">Chip top-level logic and physical design, specializing in timing-aware logical partitioning, floor planning, and fast timing closure for mixed-signal chips.</li> <li style="line-height:normal;background-color:white;margin:0.0in 0.0in 0.0in 2.0px;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">Analog and mixed-signal modeling and verification for complex ICs, emphasizing functional and timing models as well as physical abstraction generation.</li> <li style="line-height:normal;background-color:white;margin:0.0in 0.0in 0.0in 2.0px;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">Strong understanding of standard cell libraries, memory compilers, and timing constraints.</li> <li style="line-height:normal;background-color:white;margin:0.0in 0.0in 0.0in 2.0px;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">Digital library development and timing analysis.</li> <li style="line-height:normal;background-color:white;margin:0.0in 0.0in 0.0in 2.0px;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">Cadence RTL/STA/SDF gate-level verification flows.</li> <li style="line-height:normal;background-color:white;margin:0.0in 0.0in 0.0in 2.0px;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">Cadence tools (Innovus, Tempus, Encounter and Liberate) for STA and library characterization. </li> <li style="line-height:normal;background-color:white;margin:0.0in 0.0in 0.0in 2.0px;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">Standard and custom cell/IP cell library build, characterization, quality assurance, and release processes.</li> <li style="line-height:normal;background-color:white;margin:0.0in 0.0in 10.0pt 2.0px;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">Scripting languages (Tcl, Python) for automation.</li> </ul> </li> </ul> </li> </ul> </li> </ul> The ideal candidate will demonstrate the following behavioral traits: <ul style="margin-top:0.0in;margin-bottom:0.0in"> <li style="margin:0.0in 0.0in 0.0in 24.4px;line-height:115%;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">Excellent analytical, debugging, and problem-solving skills.</li> <li style="margin:0.0in 0.0in 0.0in 24.4px;line-height:115%;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">Strong attention to detail and commitment to layout quality.</li> <li style="margin:0.0in 0.0in 0.0in 24.4px;line-height:115%;font-size:11.0pt;font-family:Calibri, sans-serif;text-indent:0.4px">Effective verbal and written communication skills.</li> </ul> We are only considering candidates local to the position location and are unable to provide relocation for this position. This position is not eligible for visa sponsorship. Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, life insurance, paid vacation & holidays, tuition assistance programs, and more. #LI-PS1

Semiconductor Design Engineer (Teradyne, Costa Rica) (Alajuela, CR) @ Teradyne Inc

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