We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, <a href="http://www.teradyne.com/">Teradyne</a> companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview The Teradyne Compute Test Division Engineering team is looking for a highly-motivated, energetic, technically driven Digital Design Engineer to focus on the development of test instrumentation. Development occurs in a dynamic and challenging multi-site development environment. <div>We are seeking a Senior Semiconductor Design Engineer. In this role, you will architect and implement cutting‑edge digital and mixed‑signal designs that enable precise, high‑speed test capabilities for complex semiconductor devices. Your work will directly support innovations in advanced compute architectures, chiplet‑based systems, and high‑density interfaces, helping to ensure exceptional performance, accuracy, and reliability across Teradyne’s industry‑leading test platforms. This is a highly impactful opportunity to drive the design of future semiconductor test technologies and shape the evolution of next‑generation computing components.</div> <h1 style="margin:12.0pt 0.0in 0.0in;font-size:16.0pt;font-family:'Calibri Light', sans-serif;color:#2e74b5;font-weight:normal">Responsibilities</h1> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Architecture, design, implementation, verification, and lab validation of test instruments/systems.</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Work with Hardware, Software and Systems engineering to define scalable, high-performance, high-quality, extensible, and maintainable.</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Hands-on execution of product integration and verification testing and debug.</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Work closely with the design verification team to simulate your designs and ensure appropriate test coverage is achieved.</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Define and perform prototyping and characterization experiments.</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Act as technical lead for FPGA project teams, directing/mentoring junior engineers.</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Participate in logic design process improvement initiatives and tool evaluations.</li> </ul> All About You We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position. <h1 style="margin:12.0pt 0.0in 0.0in;font-size:16.0pt;font-family:'Calibri Light', sans-serif;color:#2e74b5;font-weight:normal">Skills/Technical Focus</h1> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Technical Focus: Digital logic design and FPGA physical design (Floor-planning, P&R, STA).</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Technologies: Xilinx and/or Intel FPGAs. Standard cell ASIC design experience is a plus. PCIe, AXI, DDRx, SERDES, USB, I2C, SPI, 10/100GE, PLL, HBM, DLL, ADC, DAC, MIPI, DisplayPort, PRBS.</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Languages: Expertise in Verilog and a scripting language (Python, TCL, PERL…) required. Familiarity with System Verilog, UVM, VHDL, C, C++ preferred.</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Operating Systems: Windows, Linux</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Development Tools: Cadence(Xcellium), Synopsys(Spyglass CDC/LINT), Xilinx(Vivado), Intel(Quartus), revision control tools(Clearcase, GIT, SVN), bug tracking tools(JIRA or other), continuous integration development methodologies and tools. </li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Understanding of design for high-speed signal integrity.</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Excellent troubleshooting, debugging, and problem solving skills.</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Solid verbal, written and presentation skills.</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Experience working in cross-functional teams designing complex systems</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Commitment to excellence, efficiency, and product quality</li> </ul> <h1 style="margin:12.0pt 0.0in 0.0in;font-size:16.0pt;font-family:'Calibri Light', sans-serif;color:#2e74b5;font-weight:normal">Education/Experience</h1> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">BS required, advanced degree preferred in electrical engineering or related field from a top university or engineering institution</li> <li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:10.0pt;font-family:'Times New Roman', serif">Minimum of 10 years of practical hardware development experience </li> </ul> This position is not eligible for visa sponsorship. Compensation: The base salary range for this role is $140,500 - $224,800. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance. Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click <a href="https://www.teradyne.com/2025-open-enrollment/" target="_blank" rel="noopener">here</a> to see details. #LI-MR1

Semiconductor Design Engineer [Teradyne, N. Reading, MA] (North Reading, MA, US) @ Teradyne Inc

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