We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, <a href="http://www.teradyne.com/">Teradyne</a> companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.Senior FPGA Architect - Compute Test Division Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results. <div style="margin:0.0in;text-align:center;line-height:15.0pt;font-size:11.0pt;font-family:Calibri, sans-serif" align="center"><hr align="center" size="0" width="100%"></div> Opportunity Overview Teradyne’s Compute Test Division develops advanced test solutions for next-generation silicon, including high-performance SoCs and accelerators powering modern compute and AI systems. We are seeking a Senior FPGA Architect to play a key role in architecting and delivering high-performance FPGA-based solutions at the heart of our test platforms. This role involves working at the intersection of FPGA design, board-level hardware, and system architecture—solving complex problems involving high-speed interfaces, tight timing margins, and system-level constraints. You will collaborate with cross-functional teams to design and deliver robust, scalable solutions that directly impact the quality and performance of cutting-edge semiconductor devices. <div style="margin:0.0in;text-align:center;line-height:15.0pt;font-size:11.0pt;font-family:Calibri, sans-serif" align="center"><hr align="center" size="0" width="100%"></div> Key Responsibilities <ul style="margin-bottom:0.0in;margin-top:0.0px" type="disc"> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Drive FPGA design from architecture through implementation and bring-up, including requirements definition and trade-off analysis</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Architect and implement high-performance FPGA solutions involving complex interfaces and subsystem integration</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Partner closely with hardware, software, and system engineering teams to deliver cohesive system-level solutions</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Lead timing closure, resource optimization, and performance tuning for advanced FPGA designs</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Define and execute validation strategies, including lab bring-up, debug, and root cause analysis using JTAG and lab instrumentation</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Contribute to PCB and system design decisions impacting FPGA performance and integration</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Develop automation and debug tools using scripting (TCL, Python) to improve design and validation workflows</li> </ul> <div style="margin:0.0in;text-align:center;line-height:15.0pt;font-size:11.0pt;font-family:Calibri, sans-serif" align="center"><hr align="center" size="0" width="100%"></div> Qualifications (Must-Have) <ul style="margin-bottom:0.0in;margin-top:0.0px" type="disc"> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">8+ years of hands-on experience in FPGA design and development</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Deep expertise in Verilog/SystemVerilog for design and debugging</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Proven experience with AMD (Xilinx) and/or Intel FPGA toolchains, including synthesis, implementation, and timing closure</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Strong understanding of digital design fundamentals and ability to interpret schematics</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Experience with high-speed interfaces such as PCIe, DDR, SerDes, or similar</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Demonstrated ability to bring up and debug FPGA designs on hardware platforms</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Experience with protocols such as AXI4, USB, I2C, SPI</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Scripting proficiency (TCL, Python) for automation and tooling</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Experience with version control systems and collaborative development workflows</li> </ul> <div style="margin:0.0in;text-align:center;line-height:15.0pt;font-size:11.0pt;font-family:Calibri, sans-serif" align="center"><hr align="center" size="0" width="100%"></div> Nice-to-Have <ul style="margin-bottom:0.0in;margin-top:0.0px" type="disc"> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Experience with SystemVerilog-based verification methodologies (UVM or similar)</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Familiarity with FPGA SoCs and embedded processor subsystems</li> </ul> <div style="margin:0.0in;text-align:center;line-height:15.0pt;font-size:11.0pt;font-family:Calibri, sans-serif" align="center"><hr align="center" size="0" width="100%"></div> What Sets You Apart <ul style="margin-bottom:0.0in;margin-top:0.0px" type="disc"> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Strong system-level thinking and ability to debug across FPGA, board, and software boundaries</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Ability to balance architectural decisions with implementation constraints</li> <li style="line-height:15.0pt;margin-top:0.0in;margin-right:0.0in;margin-bottom:8.0pt;font-size:11.0pt;font-family:Calibri, sans-serif">Excellent communication and collaboration skills in cross-functional environments</li> </ul> <div style="margin:0.0in;text-align:center;line-height:15.0pt;font-size:11.0pt;font-family:Calibri, sans-serif" align="center"><hr align="center" size="0" width="100%"></div> Compensation: The base salary range for this role is $164,800 - $263,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance. Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details. <a name="_Hlk158970239"></a>This position is located at our North Reading, MA development center. This position is not eligible for visa sponsorship. We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. #LI -MR1

Senior FPGA Architect (Compute Test, North Reading) (North Reading, MA, US) @ Teradyne Inc

About this role

Ready to apply?