About this role
<div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>About our group:</b></H2> </div><div><p><span style="font-size:11.0pt"><span><span style="font-family:'Calibri', sans-serif"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">At Seagate our mission is to build the world’s best data storage devices. </span></p> <p> </p> <p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">The Advanced Transducer Development group is a global R&D organization that develops new recording head technologies to advance areal density and enable Seagate’s HDD (Hard Disk Drive) 4 year+ product roadmap. Our process team uses state-of-the-art wafer fabrication tools and cleanroom facilities to innovate and deliver leading-edge writers and read sensors. With an emphasis on proving feasibility of new devices, processes and materials, we help build Seagate’s future time-to-market leadership. </span></p> <p> </p> <p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">If you are excited by innovative technology development, are naturally creative, and passionate about seeing ideas come to life then this could be a perfect fit for your research and development career.</span></p></span></span></span></p></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>About the role - you will:</b></H2> </div><div><p><span style="font-size:11.0pt"><span><span style="font-family:'Calibri', sans-serif"><ul> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Lead the wafer fabrication of advanced head devices from concept through component-level feasibility demonstration.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Work with the design team to translate device concepts into feasible, predictive test structures.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Lay out wafer build plans, including CAD, process module, test requirements, and success criteria.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Coordinate the work of unit process owners (deposition, litho, etch, CMP, wet process) to achieve equipment and process readiness for prototype wafer builds.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Manage wafer supply for critical experiments through wafer starts, daily WIP decisions and ownership of daily velocity and moves parametrics.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Ensure built devices meet design intent for geometry, performance, and reliability.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Detect, pareto and solve new defect modes related to new process module integration.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Explore new process techniques to define hardware paths needed for advanced capability and manufacturability.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Manage experiments, projects and wafer tracking to deliver results to the designated schedule.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Participate in transfers or promising new technologies to the product development engineering team.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Contribute to Seagate’s IP portfolio in the form of invention disclosures, patents, trade secrets, peer-reviewed journal articles, and/or white papers.</span></li> </ul></span></span></span></p></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>About you:</b></H2> </div><div><p><span style="font-size:11.0pt"><span><span style="font-family:'Calibri', sans-serif"><ul> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">You are self-motivated, intellectually curious, adept at problem solving, and have a strong attention to detail.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">You are an honest and respectful team player, capable of working in strong partnership with a diverse global group of engineers and technicians.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">You are a well-organized multitasker, able to maintain focus on day-to-day wafer processing needs but also keep a cadence of longer-term development work.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">You are interested in and able to provide leadership through early-stage growth of a young but talented engineering team.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">You maintain thorough documentation of results and can clearly present and discuss them with other staff members in engineering and management forums.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">You have a track record of innovation and problem-solving, and regularly use external resources (vendors, conferences, literature) to inspire new ideas and directions.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">You are able and eager to work in a mix of clean room and laboratory environments.</span></li> </ul></span></span></span></p></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Your experience includes:</b></H2> </div><div><p><span style="font-size:11.0pt"><span><span style="font-family:'Calibri', sans-serif"><ul> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Bachelor's Degree in Materials Science, Electrical Engineering, Physics, Applied Physics, Chemistry or related science and 12+ years of experience, or Master’s degree in Materials Science, Electrical Engineering, Physics, Applied Physics, Chemistry or related science and 8+ years of experience, or PHD and 5+ years of experience or equivalent education and experience.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Strong hands-on experience and in-depth understanding of wafer device builds in clean room or industrial wafer fab environments.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Experience in device building, including CAD layout, device build flow simulation/visualization, WIP management and wafer-scale integration of new processes.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Broad knowledge of conventional wafer unit processes (litho, deposition, etch, CMP, wet process) and prior device or process module ownership experience.</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Facility with a broad set of in-room characterization techniques including sheet film and device-level measurements (e.g. AFM, ellipsometry, 4pt probe, XRF, FIB, SEM, (S)TEM, etc).</span></li> <li><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Knowledge of standard statistical experimentation methods including hypothesis testing, DOE design and analysis and ANOVA. Familiarity with JMP or R preferred but not essential.</span></li> </ul> <p> </p> <p><strong><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">The estimated base salary range for this position is $130,375.00 - $190,000.00. The individual salary is based on work location and additional factors, including job-related skills, experience, and relevant education or training.</span></strong></p> <p> </p> <p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><br>Seagate offers comprehensive benefits to its eligible employees, including, but not limited to, , eligibility to participate in discretionary bonus program, medical, dental, vision, and life insurance, short-and long-term disability, 401(k), employee stock purchase plan, health savings account, dependent care, and healthcare spending accounts. Seagate also offers paid time off, including 12 holidays, flexible time off provided pursuant to Seagate policy, a minimum of 48 hours of paid sick leave, and 16 weeks of paid parental leave. The benefits for this position are based on a full-time schedule for a full calendar year and may differ depending on work location.</span></p></span></span></span></p></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Location:</b></H2> </div><div><p><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Our Normandale campus spans two suburbs, Edina and Bloomington, and serves as the Recording Head development and manufacturing arm of Seagate. Located in the heart of a bustling community, Seagate offers an on-site café, or if you prefer, you can drive to one of many restaurants just minutes away. Need to grab a gift over lunch time? Shopping is abundant in the area. If working out is your thing, the on-site fully equipped fitness center hosts wellness programs, outdoor activities, tournaments and group workouts. Looking for something more laid back? Reset in one of our meditation rooms, or simply take a walk around our indoor walking path. On-site cultural festivals, celebrations and community volunteer opportunities also abound.</span></p></p> <p> </p> <p><b>Location</b>: Normandale, United States<br> <b>Travel</b>: Up to 10%</p></div></div></div>