About this role
<p style="margin:0.0cm;text-align:left;font-size:11.0pt;font-family:'Times New Roman', serif"><span style="font-size:16.0pt;font-family:Arial, sans-serif;color:#c00000">Design Verification engineer:</span></p> <p style="margin:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"> </p> <p style="margin:0.0cm 0.0cm 0.0cm 18.0pt;font-size:12.0pt;font-family:'Times New Roman', serif"><u><span style="font-size:14.0pt;font-family:Arial, sans-serif">Description:</span></u></p> <p style="margin:0.0cm 0.0cm 0.0cm 18.0pt;background-color:white;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif;color:#222222">As a verification engineer at Winbond you’ll be a part of a team that develops the best in class products in the field of HW security and secured memories.</span></p> <p style="margin:0.0cm 0.0cm 0.0cm 18.0pt;background-color:white;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif;color:#222222">Our group offers a unique challenge for verification engineers which includes:</span></p> <ul style="margin-bottom:0.0cm;margin-top:0.0px"> <li style="background-color:white;margin:0.0cm 0.0cm 0.0cm 32.0px;font-size:12.0pt;font-family:'Times New Roman', serif;text-indent:8.0px"><span style="font-size:11.0pt;font-family:Arial, sans-serif;color:#222222">Working on multiple product lines including both “from scratch” and “legacy” projects.</span></li> <li style="background-color:white;margin:0.0cm 0.0cm 0.0cm 32.0px;font-size:12.0pt;font-family:'Times New Roman', serif;text-indent:8.0px"><span style="font-size:11.0pt;font-family:Arial, sans-serif;color:#222222">Working on IP products as well as SOC products and solving the unique problems each one requires.</span></li> <li style="background-color:white;margin:0.0cm 0.0cm 0.0cm 32.0px;font-size:12.0pt;font-family:'Times New Roman', serif;text-indent:8.0px"><span style="font-size:11.0pt;font-family:Arial, sans-serif;color:#222222">The chance to develop in Specman, System Verilog and various other languages.</span></li> </ul> <p style="margin:0.0cm 0.0cm 0.0cm 18.0pt;background-color:white;font-size:12.0pt;font-family:'Times New Roman', serif"> </p> <p style="margin:0.0cm 0.0cm 0.0cm 18.0pt;background-color:white;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif;color:#222222">You will be required to plan and execute the verification of complex RTL modules all the way from concept through Specification and to a final product.</span></p> <p style="margin:0.0cm 0.0cm 0.0cm 18.0pt;background-color:white;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif;color:#222222">You will work closely with experts from other disciplines such as: RT SW, Architecture, design and Validation.</span></p> <p style="margin:0.0cm 0.0cm 0.0cm 18.0pt;background-color:white;font-size:12.0pt;font-family:'Times New Roman', serif"><strong><span style="font-size:16.0pt;font-family:Arial, sans-serif;color:#0070c0"> </span></strong></p> <p style="margin:0.0cm 0.0cm 0.0cm 18.0pt;font-size:12.0pt;font-family:'Times New Roman', serif"><u><span style="font-size:14.0pt;font-family:Arial, sans-serif">Skills required:</span></u></p> <ul style="margin-top:0.0cm;margin-bottom:0.0cm" type="disc"> <li style="color:#222222;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">B.Sc in Electrical engineering, or computer science– Must.</span></li> <li style="color:#222222;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">At least 6 Years of Hardware verification experience – Must.</span></li> <li style="color:#222222;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">Experienced using Specman – Advantage</span></li> <li style="color:#222222;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">HDL knowledge – Advantage.</span></li> <li style="color:#222222;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">Good scripting capabilities - Advantage</span></li> <li style="color:#222222;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">Hands on experience with common verification methodologies, practices and tools – Must.</span></li> <li style="color:#222222;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">Quick learner – Must.</span></li> <li style="color:#222222;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">Team player - Must</span></li> </ul>