<div class="image-box"><img src="https://performancemanager5.successfactors.eu/SES/logos/4doors.jpg" style="width:700.0px"></div> <div id="p"> (Senior) Engineer, DSP Systems Engineering, meoSphere </div> PROGRAMME DESCRIPTION meoSphere is SES’s next-generation Medium Earth Orbit (MEO) satellite constellation, designed to deliver secure connectivity services to government agencies, enterprises, and commercial customers. It will also provide high-speed broadband internet to eliminate global connectivity dead zones. To accelerate development timelines, reduce costs, and ensure quality, SES is internalizing a critical segment of the satellite supply chain: the final integration of partner satellite platforms with SES’s software-defined payloads, all within a cutting-edge manufacturing and test facility. ROLE DESCRIPTION As a DSP System Engineer, you will play a key role in the design, analysis, modelling and validation of multiple signal processing blocks implemented in ASIC and FPGA technology in in our satellite payloads. Embedded in an agile software/firmware and hardware development team, you will ensure optimized algorithms and accurate modelling are implemented along the signal processing chain. In your first six months, you will model and propose algorithms for state-of-the-art Digital Beamforming ASICs and 5G NTN waveform digital processing blocks. Within two years, your algorithms and modelled systems will have flown in space, demonstrating cutting-edge digital signal processing technologies. KEY RESPONSIBILITIES / KEY RESULT AREAS <ul style="margin-top:0.0cm;margin-bottom:0.0cm" type="disc"> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Develop and model DSP algorithms for digital beamforming and channelization, MIMO, DPD, CFR, calibration, and digital compensation in phased-array and satellite communication systems.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Develop DUC/DDC blocks using multi-rate DSP techniques and ensure optimized implementation for low-power fixed point hardware (FPGA/ASIC).</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Create system-level MATLAB/Python/C++ models representing end-to-end RF and baseband processing, including beamforming algorithms, channelization, quantization effects, and channel impairments. </li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Translate high-level system requirements into implementable DSP blocks for ASIC design, collaborating with RTL and physical design teams to define fixed-point accuracy, throughput, and latency targets.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Evaluate fixed-point vs. floating-point architecture trade-offs for ASIC efficiency and precision across multiple channels.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Develop hardware/software co-design models to partition algorithms between firmware, digital logic, and analog front end.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Prototype and validate system performance via FPGA or simulation platforms; assist with pre-silicon and post-silicon validation workflows.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Optimize DSP algorithms for low power and high throughput suitable for space or high-reliability communication ASICs.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Support beamforming calibration strategies, including array calibration, gain/phase mismatch correction, and RF impairment compensation.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Generate technical reports, design documentation, and test plans to validate DSP architecture performance.</li> </ul> COMPETENCIES, QUALIFICATIONS & EXPERIENCE Required Qualifications <ul style="margin-top:0.0cm;margin-bottom:0.0cm" type="disc"> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">MS/PhD in Electrical Engineering, Signal Processing, or related field with 5 years of relevant DSP algorithm design experience.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Proven background in digital beamforming, MIMO signal processing, and calibration algorithms for phased arrays. </li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Strong experience with system-level modelling in MATLAB/Simulink and Python, including model-based design.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Proficiency in DSP algorithm simulation in C/C++ or SystemC, especially fixed-point modelling for ASIC implementation. </li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Deep understanding of OFDM, modulation schemes, adaptive filtering, channel estimation, and RF impairment modelling.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Familiarity with ASIC flow integration of DSP algorithms — RTL handoff, verification, and bit-accurate modelling.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Experience in lab-based silicon bring-up, calibration, and verification of beamforming performance.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Understanding of FPGA prototyping, hardware emulation, and verification flows used for DSP system validation.</li> </ul> Nice to have <ul style="margin-top:0.0cm;margin-bottom:0.0cm" type="disc"> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Strong grasp of digital communications theory and antenna array processing.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Capability to bridge system, algorithm, and implementation levels in custom beamforming ASICs.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Excellent communication skills for cross-functional coordination (DSP, RTL, RF, firmware, system integration).</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Analytical mindset for trade-off evaluations: precision vs. power, latency vs. accuracy, hardware cost vs. performance.</li> <li style="line-height:115%;margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:10.0pt;font-family:Arial, sans-serif">Working Experience of radiation and thermal constraints relevant to satellite ASIC system design.</li> </ul> Preferred Tools and Platforms <table class="MsoNormalTable" style="border:solid windowtext 1.0pt" border="1" cellspacing="3" cellpadding="0"> <thead> <tr> <td style="border:solid windowtext 1.0pt;padding:0.75pt 0.75pt 0.75pt 0.75pt"> Function </td> <td style="border:solid windowtext 1.0pt;padding:0.75pt 0.75pt 0.75pt 0.75pt"> Tools / Languages </td> </tr> </thead> <tbody> <tr> <td style="border:solid windowtext 1.0pt;padding:0.75pt 0.75pt 0.75pt 0.75pt"> DSP Modeling & Simulation </td> <td style="border:solid windowtext 1.0pt;padding:0.75pt 0.75pt 0.75pt 0.75pt"> MATLAB, Simulink, Python, NumPy, TensorFlow (for ML-based optimization) </td> </tr> <tr> <td style="border:solid windowtext 1.0pt;padding:0.75pt 0.75pt 0.75pt 0.75pt"> Algorithm Implementation </td> <td style="border:solid windowtext 1.0pt;padding:0.75pt 0.75pt 0.75pt 0.75pt"> C/C++, VivadoAMD </td> </tr> <tr> <td style="border:solid windowtext 1.0pt;padding:0.75pt 0.75pt 0.75pt 0.75pt"> Analysis Tools </td> <td style="border:solid windowtext 1.0pt;padding:0.75pt 0.75pt 0.75pt 0.75pt"> ADS, Keysight SystemVue, or custom DSP simulation frameworks </td> </tr> </tbody> </table> OTHER KEY REQUIREMENTS / COMMENTS <ul style="margin-bottom:0.0cm;margin-top:0.0px"> <li style="line-height:115%;margin:0.0cm 0.0cm 0.0cm 0.0px;font-size:10.0pt;font-family:Arial, sans-serif">Eligibility for ESA/EU/NATO/National SECRET personnel security clearances. Candidates must be prepared to undergo a security clearance procedure, as this position may require holding such clearance, is considered an asset.</li> <li style="line-height:115%;margin:0.0cm 0.0cm 0.0cm 0.0px;font-size:10.0pt;font-family:Arial, sans-serif">Able to travel nationally & internationally</li> </ul> The job responsibilities outlined in this document are not exhaustive and may evolve over time and be reviewed according to business needs. The salary range for this full-time position is $150,000.00 - $190,000.00 + bonus + benefits. Our salary ranges are determined by role, level, and location. The range displayed on this job posting reflects the target salary for new hires in Torrence, California. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. We understand market salaries can evolve and we are conscious that sometimes these will be open to review. <style type="text/css">div.content { background: #FFFFFF; } div.joqReqDescription { background: #FFF repeat-y!important; font-family:Arial, Helvetica, sans-serif!important; text-align:left; color:#000; width:700px!important; margin:0 auto!important; position:relative; -webkit-column-count: 1; /* Chrome, Safari, Opera */ -moz-column-count: 1; /* Firefox */ column-count: 1; padding-top:0px; padding-left: inherit; padding-bottom:50px; font-size:14px } div.joqReqDescription div.image-box { width: 700px; text-align: center; display: block; padding: 0 0 35px; } div.joqReqDescription p, div.joqReqDescription ul{ font-family:Arial, Helvetica, sans-serif!important; margin:0 15px; padding-bottom:12px; } div.joqReqDescription li{ padding-bottom:6px; } /* position: absolute; height: 389px; } div.joqReqDescription div.imagebox2 { text-align:center; } */ </style> <div id="p"> SES and its Affiliated Companies are committed to providing fair and equal employment opportunities to all. We are an Equal Opportunity employer and will consider all qualified applicants for employment without regard to race, color, religion, gender, pregnancy, sex, sexual orientation, gender identity, national origin, age, genetic information, protected veteran status, disability, or any other basis protected by local, state, or federal law. For more information on SES, click <a href="https://www.ses.com">here</a>. </div>

(Senior) Engineer, DSP Systems Engineering, meoSphere (Betzdorf, LU) @ SES

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