<div class="image-box"><img src="https://performancemanager5.successfactors.eu/SES/logos/4doors.jpg" style="width:700.0px"></div> <div id="p"> Senior Engineer, FPGA & ASIC System Architecture, meoSphere </div> The job responsibilities outlined in this document are not exhaustive and may evolve over time and be reviewed according to business needs. PROGRAMME DESCRIPTION meoSphere is the next generation of SES’s Medium Earth Orbit (MEO) satellites, delivering secure connectivity services for governments, enterprises, and commercial customers worldwide, while enabling high-speed broadband to eliminate connectivity gaps. To accelerate development, improve quality, and increase vertical integration, SES is bringing key payload development and integration capabilities in-house within a state-of-the-art manufacturing and test environment. ROLE DESCRIPTION SUMMARY We are seeking an experienced Senior Engineer, FPGA & ASIC System Architecture to drive the architecture, strategy, and delivery of advanced digital payload and radio unit solutions, based on RFSoC and AMD FPGA devices, as well as ASIC technologies. The successful candidate will act as a technical authority across multiple programs, contributing to the development of FPGA/RFSoC/Processor-based subsystems forming part of SES’s high-throughput communication systems (payloads, digital beamforming antennas, and radio units), ensuring alignment with end-to-end system requirements PRIMARY RESPONSIBILITIES / KEY RESULT AREAS <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Define and own FPGA and ASIC system architectures for RF and digital communication subsystems across multiple programs </li> </ul> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Drive architecture strategy and design consistency, ensuring reuse and scalability across platforms </li> </ul> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Translate system-level requirements into detailed architecture specifications, including: </li> </ul> <ul style="list-style-type:circle;margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 23.2667px;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Clock and reset strategies </li> </ul> <ul style="list-style-type:circle;margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 23.2667px;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Interface definitions </li> </ul> <ul style="list-style-type:circle;margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 23.2667px;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Low-level register maps </li> </ul> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Architect and specify advanced digital signal processing chains, including: </li> </ul> <ul style="list-style-type:circle;margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 23.2667px;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Beamforming </li> </ul> <ul style="list-style-type:circle;margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 23.2667px;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Digital Front-End (DFE) </li> </ul> <ul style="list-style-type:circle;margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 23.2667px;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Up/down conversion chains </li> </ul> <ul style="list-style-type:circle;margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 23.2667px;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Crest Factor Reduction (CFR) </li> </ul> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Define integration of ADC/DAC, IF signal generation, and RF signal paths, ensuring alignment with RF front-end constraints </li> </ul> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Lead high-speed data interface architecture, including Ethernet, eCPRI, and RF over Ethernet solutions </li> </ul> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Ensure compliance with relevant standards such as 3GPP (5G NR, FR2) and Radio Unit architectures </li> </ul> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Provide technical leadership across multiple FPGA and ASIC development projects, including coordination of architecture and design activities </li> </ul> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Lead and mentor RTL design teams, driving design quality, partitioning, and implementation strategies </li> </ul> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Own ASIC and FPGA requirements management, ensuring traceability, completeness, and alignment with system objectives </li> </ul> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Define and drive verification strategies and plans, ensuring robust validation from simulation to system-level testing </li> </ul> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Drive hardware bring-up, integration, and debugging activities, supporting cross-domain issue resolution </li> </ul> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Perform and validate FPGA resource estimation and performance analysis, optimizing for throughput, latency, power, and scalability </li> </ul> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Contribute to technical roadmap definition and risk mitigation strategies, including prototyping and performance validation </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Act as a technical authority and decision maker by leading complex technical activities across multiple programmes</li> </ul> QUALIFICATIONS & COMPENTENCIES <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Master’s degree or PhD in Electrical Engineering, Telecommunications, Computer Engineering, or a related field </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Significant experience (typically 10+ years) in FPGA and/or ASIC-based system design, including architecture roles </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Fluency in English; other languages are an asset</li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Proven hands-on experience with: </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">AMD/Xilinx RFSoC or similar FPGA platforms </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Complex DSP-based systems and high-performance digital architectures </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Strong expertise in: </li> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">RF digital signal processing (beamforming, DFE, conversion chains) </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">ADC/DAC interfacing and IF signal processing </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Multi-clock domain and high-speed digital design </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Solid knowledge of: </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">High-speed interfaces (Ethernet, JESD, eCPRI) </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">RF system integration and Radio Unit design </li> </ul> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Experience working with: </li> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">3GPP 5G NR / FR2 standards </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">RF over Ethernet and fronthaul architectures </li> </ul> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Proven ability to: </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Translate high-level requirements into structured architectures </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Hands-on experience in: </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Hardware bring-up, integration, and debugging </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif"><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAEAAAABCAYAAAAfFcSJAAAAAXNSR0IArs4c6QAAAARnQU1BAACxjwv8YQUAAAAJcEhZcwAADsMAAA7DAcdvqGQAAAANSURBVBhXY2BgYGAAAAAFAAGKM+MAAAAAAElFTkSuQmCC" alt="Shape" width="1" height="1"> Competencies </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Strong analytical and problem-solving mindset </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Ability to work in a multidisciplinary and international environment </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Structured, rigorous, and strategic approach to engineering </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Strong communication and leadership skills, with ability to influence at system and program level </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Proactive, autonomous, and capable of managing multiple high-impact priorities </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Strong documentation skills, including: </li> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Architecture specifications </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Verification plans </li> <li style="margin-bottom:8.0pt;line-height:107%;margin-top:0.0in;margin-right:0.0in;font-size:9.5pt;font-family:Arial, sans-serif">Technical reports </li> </ul> </ul> OTHER KEY REQUIREMENTS / COMMENTS <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">The candidate must be eligible for a “SECRET” security clearance, in accordance with the national regulations as well as EU/ESA/NATO equivalents</li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:9.5pt;font-family:Arial, sans-serif">Willing to work at least 60% onsite from office </li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:9.5pt;font-family:Arial, sans-serif">Travel as required for project realization purposes </li> </ul> Embark on a career with us, where diversity isn't just a buzzword – it's our driving force. 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Senior Engineer, FPGA & ASIC System Architecture, meoSphere (Betzdorf, LU) @ SES

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