<div class="image-box"><img src="https://performancemanager5.successfactors.eu/SES/logos/4doors.jpg" style="width:700.0px"></div> <div id="p"> Senior Engineer, FPGA, meoSphere </div> ProgramME & Role Description meoSphere is the next generation of SES’s Medium Earth Orbit (MEO) satellites. It will provide secure connectivity services for governments, enterprises, and commercial customers, while delivering high-speed broadband to eliminate connectivity dead zones. We are seeking a dynamic FPGA Engineer to join our growing aerospace team. To accelerate schedules, reduce costs, and ensure quality, SES is bringing critical payload integration activities in-house, combining partner satellite platforms with SES’s software-defined payload inside a new, state-of-the-art manufacturing and test facility. The successful candidate will contribute to the development of NGSO satellite payloads, supporting the definition of FPGA/RFSoC/Processor-based subsystems that form part of SES’s high-throughput NGSO transport network. These include regenerative on-board processors, digital beam-forming antenna subsystems, and user terminal modems. Designs may rely on FPGA, SoC, processors, COTS ASICs, or custom ASICs, and must be harmonised with the complete space payload and ground terminals (active antennas, optical terminals, on-board computers, etc.). PRIMARY RESPONSIBILITIES / KEY RESULT AREAS <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Evaluate and select radiation-tolerant FPGA/SoC/ASIC solutions for wireless system architectures, balancing throughput, cost, and power. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Implement radio access network/modem platforms for satellite communications, from system and hardware specifications through RTL design, optimising for silicon area, performance, and power. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Design and implement digital signal processing (DSP) algorithms on FPGA, meeting strict performance, power, and latency constraints. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Review, integrate, and validate third-party firmware/software developments within FPGA systems. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Define and support risk-mitigation activities, including prototype testing, lab validation, and in-orbit demonstrations. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Provide performance analysis to payload and user terminal stakeholders, supporting higher-level system design and integration. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Document design specifications, trade studies, test plans, and verification reports. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Build verification test benches and create automated end-to-end test pipelines. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Stay current with and apply communication standards relevant to satellite systems. </li> </ul> COMPETENCIES <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Strong knowledge of digital equipment development flows, focusing on high-speed DSP PCB design, interconnects, and integration/testing. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Proficiency in FPGA/SoC/Processor architecture selection and development flows. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Solid theoretical and practical background in DSP; experience designing high-speed DSP blocks across multiple power/clock domains. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Proven experience designing, implementing, and testing DSP algorithms in RTL code. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Hands-on experience with Xilinx FPGA platforms (RFSoC, Versal Gen1/Gen2). </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Expertise in optimising DSP algorithms for area, power, and performance. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Experience in high-speed logic design. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Design/verification experience with mixed-signal ICs (ADCs, DACs, modems, channelizers, beamformers), high-speed SerDes (JESD204C, PCIe, Ethernet), and low-speed interfaces (CAN, SPI, I²C, RS-422/485). </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Experience with Vivado IDE. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Experience supporting hardware bring-up and system integration. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Skilled in FPGA internal logic analyser tools (ILA, Chipscope, SignalTap). </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Scripting experience (Tcl, Python). </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Good to have: </li> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">UVM verification methodology </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Lab instruments (Logic Analyser, Oscilloscope, etc.) </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">C or MATLAB programming </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Design for fault tolerance and space reliability (e.g., SEU mitigation, system monitoring) </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">High-speed interface design (SerDes, Ethernet, PCIe) </li> </ul> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Ability to work under pressure and manage multiple priorities</li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">High sensitivity to customers’ needs and capacity to find solutions to complex technical problems and overcome obstacles to deliver a high quality of service </li> </ul> Qualifications Background and Experience <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Master’s degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">7+ years of FPGA/SoC/ASIC-based electronic equipment design, preferably in the space sector. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Hands-on experience implementing FPGA, RFSoC, ASIC, and/or processor-based designs. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Eligibility for a SECRET-level security clearance under the modified law of 15 June 2004 (and EU/ESA/NATO equivalents) is considered an asset. </li> <li style="margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">Fluency in English; other languages are an asset. </li> </ul> Other key requirements / comments <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:13.0pt;font-size:9.5pt;font-family:Arial, sans-serif">The candidate must be eligible for a “SECRET” security clearance, in accordance with the national regulations as well as EU/ESA/NATO equivalents</li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:9.5pt;font-family:Arial, sans-serif">Willing to work at least 60% onsite from office </li> <li style="line-height:normal;margin:0.0in 0.0in 0.0in 0.0px;font-size:9.5pt;font-family:Arial, sans-serif">Travel as required for project realization purposes </li> </ul> SES is an Equal Opportunity and Affirmative Action Employer <style type="text/css">div.content { background: #FFFFFF; } div.joqReqDescription { background: #FFF repeat-y!important; font-family:Arial, Helvetica, sans-serif!important; text-align:left; color:#000; width:700px!important; margin:0 auto!important; position:relative; -webkit-column-count: 1; /* Chrome, Safari, Opera */ -moz-column-count: 1; /* Firefox */ column-count: 1; padding-top:0px; padding-left: inherit; padding-bottom:50px; font-size:14px } div.joqReqDescription div.image-box { width: 700px; text-align: center; display: block; padding: 0 0 35px; } div.joqReqDescription p, div.joqReqDescription ul{ font-family:Arial, Helvetica, sans-serif!important; margin:0 15px; padding-bottom:12px; } div.joqReqDescription li{ padding-bottom:6px; } /* position: absolute; height: 389px; } div.joqReqDescription div.imagebox2 { text-align:center; } */ </style> <div id="p"> SES and its Affiliated Companies are committed to providing fair and equal employment opportunities to all. We are an Equal Opportunity employer and will consider all qualified applicants for employment without regard to race, color, religion, gender, pregnancy, sex, sexual orientation, gender identity, national origin, age, genetic information, protected veteran status, disability, or any other basis protected by local, state, or federal law. For more information on SES, click <a href="https://www.ses.com">here</a>. </div>

Senior Engineer, FPGA, MEO 1 (Betzdorf, LU) @ SES

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