About this role
Job Requirements Roles & Responsibilities • Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. • Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). • Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. • Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). • Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. • Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. • Experience in synthesis and formal equivalence checking (LEC) to ensure design quality. • Familiarity with signoff methodologies and tapeout process. • Mentor and guide junior engineers within the team, review their work, and drive best practices. • Contribute to methodology improvements, flow automation, and scripting.
⸻ Key Skills
• Strong expertise in Physical Design EDA tools: Cadence (Innovus, Voltus, Tempus, LEC ) or Synopsys (PrimeTime, StarRC) • Hands-on with STA, Power, and Area optimization techniques. • Proficiency in scripting (Perl/Tcl/Shell) for automation and flow enhancements. • Experience with low power design techniques (UPF/CPF), multi-voltage domains, and advanced nodes (3nm/5nm/22nm/28nm as applicable). • Solid understanding of physical verification and signoff (Calibre or equivalent).
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Desired Profile
• B.E./B.Tech/M.E./M.Tech in Electronics, or related field. • 7–11 years of relevant experience in Physical Design on large SoC/ASIC projects. • Proven track record of successful tapeouts in advanced technology nodes. • Good problem-solving skills and ability to work independently and as part of a team.
• Able to handle a small team of 4 members along with hands on • Excellent communication and documentation skills.
Work Experience
• Strong expertise in Physical Design EDA tools: Cadence (Innovus, Voltus, Tempus, LEC ) or Synopsys (PrimeTime, StarRC) • Hands-on with STA, Power, and Area optimization techniques. • Proficiency in scripting (Perl/Tcl/Shell) for automation and flow enhancements. • Experience with low power design techniques (UPF/CPF), multi-voltage domains, and advanced nodes (3nm/5nm/22nm/28nm as applicable). • Solid understanding of physical verification and signoff (Calibre or equivalent).