About this role
Lead RTL Design Engineer ( Mixed-Signal IPs) at Silabs. Location: Hyderabad, Telangana, India. Role: developing RTL, integrating IPs, verifying designs Requirements: 5–10 years RTL design experience; proficiency in Verilog/SystemVerilog, synthesis and static verification (lint, CDC); familiarity with mixed-signal concepts and co-simulation tools; experience with SPI/I2C/APB/AXI and scripting (Python, Perl, TCL). Category: Engineering Seniority: Senior Level Tools: Verilog, SystemVerilog, Cadence AMS Designer, Synopsys VCS AMS, SPI, I2C, APB, AXI, Python, Perl, TCL Commitment: Full Time Workplace: Onsite Languages: English