About this role
Staff Design Verification Engineer at Analog Devices. Location: Edinburgh, Scotland, United Kingdom. Role: verifying designs, supporting validation, improving methodologies Requirements: Electronics degree with 7+ years experience in mixed-signal/full-chip verification, DMS SV/UVM, gate-level simulation, RNM/Verilog-AMS modeling, Cadence tools, scripting (Shell/TCL/Perl/Python), FPGA prototyping, and multi-clock/power domain experience. Category: Engineering Seniority: Senior Level Tools: Cadence, Xcelium, IMC, Virtuoso, ePlanner, vManager, Shell, TCL, Perl, Python, Verilog-AMS, RNM, FPGA Commitment: Full Time Workplace: Onsite Languages: English