About this role
Senior Staff- IP RTL Design Engineer at Marvell. Location: Bangalore, Karnataka, India. Role: designing rtl, architecting ip, mentoring engineers Requirements: 8+ years digital IC design experience delivering silicon‑proven IP/SoCs; BSEE/MSEE or equivalent; hands‑on SystemVerilog/Verilog; experience with high‑speed interfaces (UCIe/HBM/PCIe/etc.), RTL sign‑off flows, synthesis/STA/formal, and mentoring skills. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, Verilog, VHDL, SpyGlass Commitment: Full Time Workplace: Onsite Languages: English