About this role
[Permanent position] Senior verification engineer / team lead at SiPearl. Location: Maisons-Laffitte or Massy or Grenoble or Castelldefels or Bologna. Role: define platform, develop tests, lead team Requirements: 7–10 years ASIC/SoC verification; 3–5 years as architect/lead; SystemVerilog/UVM, VHDL/Verilog, C/C++, Python; team management; strong SoC architectures and protocols; fluent French and professional English Category: Software Development Seniority: Senior Level Tools: SystemVerilog, UVM, VHDL, Verilog, C, C++, Python, TCL, AXI, AHB, PCIe, Ethernet Commitment: Full Time Workplace: Hybrid Languages: French, English