About this role
APAC Algo Trading Low Latency FPGA/C++ Developer at UBS Group AG. Location: Shanghai or China. Role: designing FPGA, implementing C++, optimizing latency Requirements: 7+ years FPGA (Verilog/VHDL) or low-latency C++ development; expert C++17/20/23, Linux system programming, concurrency, FPGA toolchains (Vivado/Quartus), high-speed networking, and experience with trading protocols. Category: Software Development Seniority: Senior Level Tools: C++17, C++20, C++23, Linux, Vivado, Quartus, Verilog, VHDL, Rivermax, FIX, ITCH, RoCEv2, FPGA Commitment: Full Time Workplace: Onsite Languages: English