About this role
Memory Design Engineer at Allegro MicroSystems. Location: Buenos Aires, Buenos Aires, Argentina. Role: Design memory IP, Test and validate IP in silicon, Coordinate layout and floorplanning Requirements: BSEE with 2+ years in memory/mixed-signal design, circuit verification, and silicon testing; experience with CAD/EDA tools, HDL (Verilog) and memory/IP development. Category: Engineering Seniority: Entry Level Tools: Cadence Virtuoso, Genus, Innovus, Xcellium, Modus Test, Calibre, Verilog, SystemVerilog, HDL Commitment: Full Time Workplace: Onsite Languages: English