About this role
Senior VLSI Design Engineer at Istra LLC. Location: Lod, Central District, Israel. Role: designing systems, owning architecture, debugging issues Requirements: BSc/MSc in Computer/Electrical Engineering, 5+ years hardware design experience, HDL (Verilog/System Verilog/VHDL), FPGA/Xilinx experience preferred, HW-SW integration, lab debugging; C/C++ and Python/R/Tcl are advantages. Category: Engineering Seniority: Senior Level Tools: HDL, Verilog, System Verilog, VHDL, FPGA, Xilinx, C, C++, Python, R, Tcl Commitment: Full Time Workplace: Onsite Languages: English