About this role
Silicon Engineer at Sine Engineering. Location: Tampere, Finland, Finland. Role: designing RTL, verifying blocks, bringing up SoC Requirements: Digital design or verification background; RTL/SystemVerilog/VHDL; SoC concepts; English B1+. Category: Engineering Seniority: Mid Level Tools: Verilog, SystemVerilog, VHDL, UVM, Python, Tcl, Perl, AXI, AHB, MIPI, LVDS Commitment: Full Time Workplace: Onsite Languages: English