About this role
FPGA Verification Engineer - Avionics at Espace. Location: Saratoga, California, United States. Role: Develop UVM environments, Create reusable UVM framework, Write verification plans Requirements: 4+ years FPGA/ASIC verification; SystemVerilog/UVM; develop verification environments; RTL simulation; functional coverage; timing analysis. Category: Engineering Seniority: Mid Level Tools: SystemVerilog, UVM, RTL simulators, VCS, QuestaSim, Python, TCL, lint, CDC analysis tools Commitment: Full Time Workplace: Onsite Languages: English