About this role
FPGA Engineer at Tekeyer. Location: Porto, /, Portugal. Role: Leading feasibility, Defining requirements, Designing FPGA Requirements: 2+ years in FPGA development for high-throughput digital systems; strong DSP/communication theory; HDL (VHDL/Verilog/SystemVerilog); Python/MATLAB; English proficiency; team collaboration. Category: Engineering Seniority: Mid Level Tools: HDL, VHDL, Verilog, SystemVerilog, FPGA, SoC, Python, MATLAB Commitment: Full Time Workplace: Hybrid Languages: English, Portuguese