About this role
Senior ASIC Physical Design Engineer at K2 Space. Location: United States. Role: implementing SoCs, optimizing timing, supporting integration Requirements: Bachelor's or Master's in EE/Computer Engineering, 5+ years ASIC physical design experience, hands-on with Synopsys ICC2/Fusion Compiler or Cadence Innovus, timing/power/physical verification expertise, DFT and power-intent knowledge. Category: Engineering Seniority: Senior Level Tools: Synopsys ICC2, Synopsys Fusion Compiler, Cadence Innovus, GDSII, DRC, LVS, IR drop, EM, CTS, STA, DFT, UPF, CPF, TSMC Commitment: Full Time Workplace: Remote Languages: English